1 - BRK - Software Break

BRK forces a software interrupt. It is unaffected by the i interrupt disable flag.

The BRK instruction is a single byte instruction. However, when it is invoked the Program Counter is incremented by 2. This allows for a one-byte signature value indicating which break caused the interrupt.

Even if the signature byte is not required, it must either be there or the RTI instruction which returns control to the caller must manually decrement the return address. As this can be tricky, most operating systems require BRK to take up 2 bytes in memory.

6502, 65C02 & Emulation Mode (e=1)

The program counter is incremented by two & pushed onto the stack. The status register (with b break flag set) is pushed onto the stack. The interrupt disable flag is then set, disabling interrupts. The program counter is loaded with the interrupt vector at &FFFE-&FFFF.

It's up to the interrupt handler pointed to by (&FFFE) to test the b flag to determine if the interrupt was from a software (BRK) rather than a hardware (IRQ) interrupt.

 1.handler PLA       ; copy status from stack
 2         PHA       ; but don't remove it else RTI will break
 3
 4         AND #&10  ; check B flag
 5         BNE isBrk ; call break handler
 6
 7.isIRQ             ; hardware handler here
 8         RTI       ; exit hardware handler
 9
10.isBrk             ; break handler here
11         RTI       ; exit BRK handler

65802/65816 Native Mode (e=0)

The program bank register is pushed onto the stack. The program counter is incremented by two & pushed onto the stack. The status register is pushed onto the stack. The interrupt disable flag is then set, disabling interrupts. The program counter is loaded with the break vector at &00FFE6-&00FFE7.

Decimal Mode

On the 6502 the decimal d flag is not modified after a BRK is executed. On the 65C02 & 65816 the decimal d flag is reset to 0.

1.1 - BRK on the BBC Micro & Acorn Electron

In the operating system for the BBC Micro (& Acorn Electron), the standard is to write BRK followed by an error number, then the error message ending with a 0

1BRK           ; Software break
2EQUB 0        ; Error code
3EQUS "Silly"  ; This is a real error message in BBC BASIC, try: AUTO10,1000
4EQUB 0        ; End of message marker

Service ROM's usually write error messages into RAM starting at &0100 and then do a JMP &0100 to run it. They do that as the handler is usually in a Language rom so they would be paged out if they ran BRK from their own ROM.

2 - COP - Co-Processor Enable

COP causes a software interrupt similar to BRK but through a separate vector. Unlike BRK, it is possible for it to be trapped by an optional co-processor like a floating point processor or a graphics processor. It is unaffected by the i interrupt disable flag.

Like BRK, COP increments the Program Counter by 2. However assemblers require the second byte to be provided as part of the instruction.

Values &00-&7F are free for use by software handlers.

Values &80-&FF are reserved for hardware implementations.

65802/65816 in 6502 emulation mode (e=1)

The program counter is incremented by two & pushed onto the stack. The status register is pushed onto the stack. The interrupt disable flag is then set, disabling interrupts. The program counter is loaded with the interrupt vector at &FFF4-&FFF5. The d flag is reset to 0 after the instruction is executed.

65802/65816 in native mode (e=0)

The program bank register is pushed onto the stack. The program counter is incremented by two & pushed onto the stack. The status register is pushed onto the stack. The interrupt disable flag is then set, disabling interrupts. The program bank register is set to 0. The program counter is loaded with the break vector at &00FFE4-&00FFE5. The d flag is reset to 0 after the instruction is executed.

3 - RTI

The RTI instruction is used at the end of an interrupt handler. It pulls both the status register and program counter from the stack. For 16bit processors running in native mode it also pulls the program bank register from the stack.

Unlike RTS, the address on the stack is the actual return address. (RTS expects it to be the address before the next instruction).

4 - WAI - Wait for Interrupt

WAI pulls the RDY pin low. Power consumption reduced to a minimum and RDY is kept low until an external hardware interrupt (NMI, IRQ, ABORT or RESET) is received.

When an interrupt is received

Interrupts enabled i=0

When a hardware interrupt is received, control is vectored though one of the hardware interrupt vectors. An RTI instruction in the invoked handler will return control back to the instruction immediately after the WAI.

Interrupts disabled i=1

If interrupts were disabled at the time WAI was invoked then when the interrupt is received then the relevant interrupt handler is not called and execution resumes immediately with the instruction after the WAI. This allows for processing to be synchronized with the interrupt.

The data bus

As WAI pulls RDY low it frees up the bus. If BE is also pulled low, the processor can be disconnected from the bus.