COP causes a software interrupt similar to BRK but through a separate vector. Unlike BRK, it is possible for it to be trapped by an optional co-processor like a floating point processor or a graphics processor. It is unaffected by the i interrupt disable flag.

Like BRK, COP increments the Program Counter by 2. However assemblers require the second byte to be provided as part of the instruction.

Values &00-&7F are free for use by software handlers.

Values &80-&FF are reserved for hardware implementations.

65802/65816 in 6502 emulation mode (e=1)

The program counter is incremented by two & pushed onto the stack. The status register is pushed onto the stack. The interrupt disable flag is then set, disabling interrupts. The program counter is loaded with the interrupt vector at &FFF4-&FFF5. The d flag is reset to 0 after the instruction is executed.

65802/65816 in native mode (e=0)

The program bank register is pushed onto the stack. The program counter is incremented by two & pushed onto the stack. The status register is pushed onto the stack. The interrupt disable flag is then set, disabling interrupts. The program bank register is set to 0. The program counter is loaded with the break vector at &00FFE4-&00FFE5. The d flag is reset to 0 after the instruction is executed.