1 - Block Move

The MVN & MVP instructions moves/copies a block of memory from one location to another.

The source, destination and length of the block are taken from the X, Y & C registers.

The source address is in X, the destination address is in Y.

The length of the block minus 1 is in the C double accumulator. So if you are moving 42 bytes then C should have 41.

The two bytes of the operand consists of the source bank in the first byte and the destination bank in the second.

Processor modes

These instructions should be run in 16-bit native mode. If the index registers are in 8-bit mode (x=1) or the processor is in 6502 emulation mode (e=1) then the blocks specified will be in zero page due to the high byte of the index registers will be 0.

Interrupts

If a block move instruction is interrupted, it may be resumed automatically when RTI is executed by the handler, as long as the registers are left intact. The address pushed to the stack when it is interrupted is the address of the block move instruction so it resumes where it left off. The byte currently being moved will complete first before the interrupt is serviced.

MVN

MVN copies a block from the start of the source block to the start of the destination block.

The source and destination addresses need to point to the first byte of each block to be moved.

When execution is complete, the C accumulator will be &FFFF X & Y will point to the byte after the end of the source & destination blocks respectively.

MVP - Block Move Previous

MVP copies a block from the end of the source block to the end of the destination block.

The source and destination addresses need to point to the last byte of each block to be moved.

When execution is complete, the C accumulator will be &FFFF X & Y will point to the byte before the start of the source & destination blocks respectively.

2 - XCE

This instruction is the only means to shift a 65802 or 65812 processor between 6502 emulation mode and full 16-bit native mode.

Switch to native 16-bit mode

To switch into native mode, clear the carry bit then invoke XCE

1.goNative
2    CLC      ; Clear Carry to indicate native mode
3    XCE      ; Processor will be in 16-bit native mode once this completes
4    RTS      ; Carry will now set if we were originally in emulation or clear if already native.

Once XCE has completed and the processor is in native mode, the following would have occurred.

• bit 5 of the flags stops being the b break flag. It's now the x mode select flag
• bit 6 is now the m memory mode flag (it's unused in 6502 emulation mode)
• Both x & m are set to 1

Switch to 6502 emulation mode

To switch into 6502 emulation mode, set the carry bit then invoke XCE

1.goEmulation
2    SEC      ; Set Carry to indicate native mode
3    XCE      ; Processor will be in 16-bit native mode once this completes
4    RTS      ; Carry will now set if we were already in emulation or clear if we were originally native.

Once XCE has completed and the processor is in 6502 emulation mode, the following would have occurred.

• The x & m flags are lost from the status register.
• bit 6 is unavailable as it's unused in 6502 emulation mode
• The accumulator is forced into 8-bit's, the high 8 bits are in the hidden B accumulator
• The index registers are forced into 8-bits. The high 8-bits are lost.
• The stack pointer is forced into page 1, losing the high byte of the address.

3 - NOP

A NOP takes no action and does not effect any registers except the program counter.

NOP's are usually used for timing loops as each NOP takes 2 cycles.

4 - Reserved

The 65802 & 654816 processors use 255 out of the possible 256 8-bit opcodes. The remaining opcode is this one, labeled WDM which happens to be the initials of William D. Mensch who designed the processors.

To allow additional instructions to be added later this instruction act's as a prefix allowing an additonal 256 opcodes. This is a similar technique to the Z80 & 8080 processors which have 2-byte extension opcodes.

The actual number of bytes and cycles involved will be depended on those extensions, however the byte size will be a minimum of 2 bytes.

On the 65802 & 65816 this instruction will execute as a 2-byte NOP.

5 - STP - Stop Processor

STP will stop the processors oscillator input, shutting down the processor until a reset occurs by pulling the RES pin low.

As power consumption is a function of frequency in CMOS circuits, stopping the clock cuts power to almost nothing.