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Load the accumulator with data from memory.
On all processors, the data loaded from memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data added is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.
Flags |
| ||||||||
---|---|---|---|---|---|---|---|---|---|
n | Set if most-significant bit of result is set | ||||||||
z | Set if result is zero |
Syntax | Opcode | Available on: | # of | # of | Addressing Mode | ||
---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | ||
LDA #const | A9 | x | x | x | 21 | 22 | Immediate |
LDA addr | AD | x | x | x | 3 | 42 | Absolute |
LDA long | AF | x | 4 | 52 | Absolute Long | ||
LDA dp | A5 | x | x | x | 2 | 32, 3 | Direct Page |
LDA (dp) | B2 | x | x | 2 | 52, 3 | Direct Page Indirect | |
LDA [dp] | A7 | x | 2 | 62, 3 | Direct Page Indirect Long | ||
LDA addr,X | BD | x | x | x | 3 | 42, 4 | Absolute Indexed X |
LDA long,X | BF | x | 4 | 52 | Absolute Long Indexed X | ||
LDA addr,Y | B9 | x | x | x | 3 | 42, 4 | Absolute Indexed Y |
LDA dp,X | B5 | x | x | x | 2 | 42, 3 | Direct Page Indexed X |
LDA (dp,X) | A1 | x | x | x | 2 | 62, 3 | Direct Page Indexed Indirect X |
LDA (dp),Y | B1 | x | x | x | 2 | 52, 3, 4 | Direct Page Indirect Indexed Y |
LDA [dp],Y | B7 | x | 2 | 62, 3 | Direct Page Indirect Long Indexed Y | ||
LDA sr,S | A3 | x | 2 | 42 | Stack Relative | ||
LDA (sr,S),Y | B3 | x | 2 | 72 | Stack Relative Indirect Indexed Y |
Load index register X with data from memory.
On all processors, the data loaded from memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data added is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.
Flags |
| ||||||||
---|---|---|---|---|---|---|---|---|---|
n | Set if most-significant bit of result is set | ||||||||
z | Set if result is zero |
Syntax | Opcode | Available on: | # of | # of | Addressing Mode | ||
---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | ||
LDX #const | A2 | x | x | x | 21 | 22 | Immediate |
LDX addr | AE | x | x | x | 3 | 42 | Absolute |
LDX dp | A6 | x | x | x | 2 | 32, 3 | Direct Page |
LDX addr,X | BE | x | x | x | 3 | 42, 4 | Absolute Indexed X |
LDX dp,X | B6 | x | x | x | 2 | 42, 3 | Direct Page Indexed X |
Load index register Y with data from memory.
On all processors, the data loaded from memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data added is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.
Flags |
| ||||||||
---|---|---|---|---|---|---|---|---|---|
n | Set if most-significant bit of result is set | ||||||||
z | Set if result is zero |
Syntax | Opcode | Available on: | # of | # of | Addressing Mode | ||
---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | ||
LDY #const | A0 | x | x | x | 21 | 22 | Immediate |
LDY addr | AC | x | x | x | 3 | 42 | Absolute |
LDY dp | A4 | x | x | x | 2 | 32, 3 | Direct Page |
LDY addr,X | BC | x | x | x | 3 | 42, 4 | Absolute Indexed X |
LDY dp,X | B4 | x | x | x | 2 | 42, 3 | Direct Page Indexed X |
Stores the accumulator into memory.
On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.
None. |
Syntax | Opcode | Available on: | # of | # of | Addressing Mode | ||
---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | ||
STA addr | 8D | x | x | x | 3 | 41 | Absolute |
STA long | 8F | x | 4 | 51 | Absolute Long | ||
STA dp | 85 | x | x | x | 2 | 31, 2 | Direct Page |
STA (dp) | 92 | x | x | 2 | 51, 2 | Direct Page Indirect | |
STA [dp] | 87 | x | 2 | 61, 2 | Direct Page Indirect Long | ||
STA addr,X | 9D | x | x | x | 3 | 41 | Absolute Indexed X |
STA long,X | 9F | x | 4 | 51 | Absolute Long Indexed X | ||
STA addr,Y | 99 | x | x | x | 3 | 41 | Absolute Indexed Y |
STA dp,X | 95 | x | x | x | 2 | 41, 2 | Direct Page Indexed X |
STA (dp,X) | 81 | x | x | x | 2 | 61, 2 | Direct Page Indexed Indirect X |
STA (dp),Y | 91 | x | x | x | 2 | 51, 2 | Direct Page Indirect Indexed Y |
STA [dp],Y | 97 | x | 2 | 61, 2 | Direct Page Indirect Long Indexed Y | ||
STA sr,S | 83 | x | 2 | 41 | Stack Relative | ||
STA (sr,S),Y | 93 | x | 2 | 71 | Stack Relative Indirect Indexed Y |
Stores the index register X into memory.
On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.
None. |
Syntax | Opcode | Available on: | # of | # of | Addressing Mode | ||
---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | ||
STX addr | 8E | x | x | x | 3 | 41 | Absolute |
STX dp | 86 | x | x | x | 2 | 31, 2 | Direct Page |
STX dp,Y | 96 | x | x | x | 2 | 41, 2 | Direct Page Indexed Y |
Stores the index register Y into memory.
On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.
None. |
Syntax | Opcode | Available on: | # of | # of | Addressing Mode | ||
---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | ||
STY addr | 8C | x | x | x | 3 | 41 | Absolute |
STY dp | 84 | x | x | x | 2 | 31, 2 | Direct Page |
STY dp,X | 94 | x | x | x | 2 | 41, 2 | Direct Page Indexed X |
Stores zero to memory.
On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.
None. |
Syntax | Opcode | Available on: | # of | # of | Addressing Mode | ||
---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | ||
STZ addr | 9C | x | x | 3 | 41 | Absolute | |
STZ dp | 64 | x | x | 2 | 31, 2 | Direct Page | |
STZ addr,X | 9E | x | x | 3 | 51 | Absolute Indexed X | |
STZ dp,X | 74 | x | x | 2 | 41, 2 | Direct Page Indexed X |
The transfer register set of instructions allows for data to be passed between different registers.
In all of these transfer instructions, the source register is unchanged.
For example, on the 6502 to save the X register on the stack you would need to use the following:
1TXA ; Transfer X into A
2PHA ; Push A to the stack
Note: On the 65C02 and later this is replaced by the PHX instruction which doesn't touch the accumulator.
Transfers the Accumulator to X. On the 8-bit processors the registers are all the same size, however on the 16-bit processors the registers can be of different sizes. The following table describes how the data is transferred when a size mismatch occurs:
Source Size | Dest Size | m | x | Action performed |
---|---|---|---|---|
8 | 8 | All types | Value transferred is 8-bit | |
8 | 16 | 1 | 0 |
Value transferred is 16-bit. The 8-bit A becomes the low byte of the index register. The 8-bit hidden B register becomes the high byte of the index register. |
16 | 8 | 0 | 1 | The low byte of A is transferred to the index register |
16 | 16 | 0 | 0 | The full 16-bit A is transferred to the index register |
Transfers the Accumulator to Y. It follows the same rules as TAX.
TCD transfers the 16-bit accumulator C to the direct page register D, regardless of the accumulator/memory flag.
The C accumulator is used to indicate that 16-bits are transferred regardless of the m flag. If the A accumulator is 8-bit due to m=1 or in 6502 emulation mode then C = A as the low 8-bits and the hidden B accumulator as the high 8-bits.
TCS transfers the 16-bit accumulator C to the stack pointer S, regardless of the accumulator/memory flag. The C register is defined above for TCD. An alternate mnemonic for TCS is TAS.
Note: Unlike most transfer instructions, TCS does not affect any flags.
TDC transfers the Direct Page Register to the 16-bit accumulator C. The C register is defined above for TCD. An alternate mnemonic for TDC is TDA.
TSC transfers the stack pointer S to the 16-bit accumulator C, regardless of the accumulator/memory flag. The C register is defined above for TCD. An alternate mnemonic for TCS is TSA.
TSX transfers the stack pointer to X. The stack pointer is unchanged. On 8-bit processors only the low byte is transferred to X. On 16-bit processors (x=0) the full 16-bit value is tranferred to X.
TXA transfers X into the accumulator. On the 8-bit processors the registers are all the same size, however on the 16-bit processors the registers can be of different sizes. The following table describes how the data is transferred when a size mismatch occurs:
Source Size | Dest Size | m | x | Action performed |
---|---|---|---|---|
8 | 8 | All types | Value transferred is 8-bit | |
8 | 16 | 1 | 0 |
Value transferred is 16-bit. The 8-bit index register becomes the low byte of the accumulator. The high-byte of the accumulator is set to 0. |
16 | 8 | 0 | 1 |
Value transferred is 8-bit. The low 8-bits of the index register becomes the low byte of the accumulator. The high-byte of the hidden accumulator B is not affected by the transfer. |
16 | 16 | 0 | 0 | The full 16-bit index register is transferred to the accumulator |
TXS transfers X to the stack pointer to. The X is unchanged. On 8-bit processors only the low byte is transferred to S. On 16-bit processors (x=1) the low 8-bits of X is transferred to S. The high 8-bits of S are zeroed. On 16-bit processors (x=0) the full 16-bit value of X is transferred to S.
Note: Unlike most transfer instructions, TXS does not affect any flags.
TXY transfers X to Y. X is unchanged. The registers are always the same size, so when 8-bit then that's what's transferred. When 16-bit (x=0) then 16-bits are transferred.
TYA transfers Y into the accumulator. It follows the same rules as TXA above.
TYX transfers Y to X. Y is unchanged. The registers are always the same size, so when 8-bit then that's what's transferred. When 16-bit (x=0) then 16-bits are transferred.
On the 16-bit processors the 16-bit C accumulator is formed of two 8-bit accumulators, A for the low 8-bits and B for the upper 8-bits. XBA swaps the contents of the A & B registers.
In 8-bit memory mode, B is usually referred to as the hidden B accumulator, so the XBA instruction can be used to swap the accessible A with B, providing an in-processor scratch accumulator rather than pushing a value to the stack.
The flags are based on the value of the 8-bit A accumulator
Flags |
| ||||||||
---|---|---|---|---|---|---|---|---|---|
n | Set if most significant bit of the transferred value is set | ||||||||
z | Set if value transferred is zero |
Src | Dest | Syntax | Opcode | Available on: | # of | # of | Addressing Mode | Notes | ||
---|---|---|---|---|---|---|---|---|---|---|
(hex) | 6502 | 65C02 | 65816 | bytes | cycles | |||||
A | X | TAX | AA | x | x | x | 1 | 2 | Implied | |
A | Y | TAY | A8 | x | x | x | 1 | 2 | Implied | |
C | D | TCD | 5B | x | 1 | 2 | Implied | |||
C | S | TCS | 1B | x | 1 | 2 | Implied | Flags are unaffected | ||
D | C | TDC | 7B | x | 1 | 2 | Implied | |||
S | C | TSC | 3B | x | 1 | 2 | Implied | |||
S | X | TSX | BA | x | x | x | 1 | 2 | Implied | |
X | A | TXA | 8A | x | x | x | 1 | 2 | Implied | |
X | S | TXS | 9A | x | x | x | 1 | 2 | Implied | Flags are unaffected |
X | Y | TXY | 9B | x | 1 | 2 | Implied | |||
Y | A | TYA | 98 | x | x | x | 1 | 2 | Implied | |
Y | X | TYX | BB | x | 1 | 2 | Implied | |||
B | A | XBA | EB | x | 1 | 2 | Implied | Exchanges both registers, flags based on A post exchange |