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Registers

Register operations

Table of Contents

1 - LDA

Load Accumulator from Memory

Load the accumulator with data from memory.

On all processors, the data loaded from memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data added is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.

Flags Affected
Flags
n-----z-
nSet if most-significant bit of result is set
zSet if result is zero
Instructions
SyntaxOpcode Available on: # of # of Addressing Mode
(hex) 6502 65C02 65816 bytes cycles
LDA #constA9 x x x 21 22 Immediate
LDA addrAD x x x 3 42 Absolute
LDA longAF x 4 52 Absolute Long
LDA dpA5 x x x 2 32, 3 Direct Page
LDA (dp)B2 x x 2 52, 3 Direct Page Indirect
LDA [dp]A7 x 2 62, 3 Direct Page Indirect Long
LDA addr,XBD x x x 3 42, 4 Absolute Indexed X
LDA long,XBF x 4 52 Absolute Long Indexed X
LDA addr,YB9 x x x 3 42, 4 Absolute Indexed Y
LDA dp,XB5 x x x 2 42, 3 Direct Page Indexed X
LDA (dp,X)A1 x x x 2 62, 3 Direct Page Indexed Indirect X
LDA (dp),YB1 x x x 2 52, 3, 4 Direct Page Indirect Indexed Y
LDA [dp],YB7 x 2 62, 3 Direct Page Indirect Long Indexed Y
LDA sr,SA3 x 2 42 Stack Relative
LDA (sr,S),YB3 x 2 72 Stack Relative Indirect Indexed Y

Notes:

  1. 65816: Add 1 byte if m=0 (16-bit memory/accumulator)
  2. 65816: Add 1 cycle if m=0 (16-bit memory/accumulator)
  3. 65816: Add 1 cycle if low byte of Direct Page register is not 0
  4. Add 1 cycle if adding index crosses a page boundary

2 - LDX

Load Index Register X from Memory

Load index register X with data from memory.

On all processors, the data loaded from memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data added is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.

Flags Affected
Flags
n-----z-
nSet if most-significant bit of result is set
zSet if result is zero
Instructions
SyntaxOpcode Available on: # of # of Addressing Mode
(hex) 6502 65C02 65816 bytes cycles
LDX #constA2 x x x 21 22 Immediate
LDX addrAE x x x 3 42 Absolute
LDX dpA6 x x x 2 32, 3 Direct Page
LDX addr,XBE x x x 3 42, 4 Absolute Indexed X
LDX dp,XB6 x x x 2 42, 3 Direct Page Indexed X

Notes:

  1. 65816: Add 1 byte if m=0 (16-bit memory/accumulator)
  2. 65816: Add 1 cycle if m=0 (16-bit memory/accumulator)
  3. 65816: Add 1 cycle if low byte of Direct Page register is not 0
  4. Add 1 cycle if adding index crosses a page boundary

3 - LDY

Load Index Register Y from Memory

Load index register Y with data from memory.

On all processors, the data loaded from memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data added is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.

Flags Affected
Flags
n-----z-
nSet if most-significant bit of result is set
zSet if result is zero
Instructions
SyntaxOpcode Available on: # of # of Addressing Mode
(hex) 6502 65C02 65816 bytes cycles
LDY #constA0 x x x 21 22 Immediate
LDY addrAC x x x 3 42 Absolute
LDY dpA4 x x x 2 32, 3 Direct Page
LDY addr,XBC x x x 3 42, 4 Absolute Indexed X
LDY dp,XB4 x x x 2 42, 3 Direct Page Indexed X

Notes:

  1. 65816: Add 1 byte if m=0 (16-bit memory/accumulator)
  2. 65816: Add 1 cycle if m=0 (16-bit memory/accumulator)
  3. 65816: Add 1 cycle if low byte of Direct Page register is not 0
  4. Add 1 cycle if adding index crosses a page boundary

4 - STA

Store Accumulator to Memory

Stores the accumulator into memory.

On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.

Flags Affected
None.
Instructions
SyntaxOpcode Available on: # of # of Addressing Mode
(hex) 6502 65C02 65816 bytes cycles
STA addr8D x x x 3 41 Absolute
STA long8F x 4 51 Absolute Long
STA dp85 x x x 2 31, 2 Direct Page
STA (dp)92 x x 2 51, 2 Direct Page Indirect
STA [dp]87 x 2 61, 2 Direct Page Indirect Long
STA addr,X9D x x x 3 41 Absolute Indexed X
STA long,X9F x 4 51 Absolute Long Indexed X
STA addr,Y99 x x x 3 41 Absolute Indexed Y
STA dp,X95 x x x 2 41, 2 Direct Page Indexed X
STA (dp,X)81 x x x 2 61, 2 Direct Page Indexed Indirect X
STA (dp),Y91 x x x 2 51, 2 Direct Page Indirect Indexed Y
STA [dp],Y97 x 2 61, 2 Direct Page Indirect Long Indexed Y
STA sr,S83 x 2 41 Stack Relative
STA (sr,S),Y93 x 2 71 Stack Relative Indirect Indexed Y

Notes:

  1. 65816: Add 1 cycle if m=0 (16-bit memory/accumulator)
  2. 65816: Add 1 cycle if low byte of Direct Page register is not 0

5 - STX

Store Index Register X to Memory

Stores the index register X into memory.

On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.

Flags Affected
None.
Instructions
SyntaxOpcode Available on: # of # of Addressing Mode
(hex) 6502 65C02 65816 bytes cycles
STX addr8E x x x 3 41 Absolute
STX dp86 x x x 2 31, 2 Direct Page
STX dp,Y96 x x x 2 41, 2 Direct Page Indexed Y

Notes:

  1. 65816: Add 1 cycle if m=0 (16-bit memory/accumulator)
  2. 65816: Add 1 cycle if low byte of Direct Page register is not 0

6 - STY

Store Index Register X to Memory

Stores the index register Y into memory.

On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.

Flags Affected
None.
Instructions
SyntaxOpcode Available on: # of # of Addressing Mode
(hex) 6502 65C02 65816 bytes cycles
STY addr8C x x x 3 41 Absolute
STY dp84 x x x 2 31, 2 Direct Page
STY dp,X94 x x x 2 41, 2 Direct Page Indexed X

Notes:

  1. 65816: Add 1 cycle if m=0 (16-bit memory/accumulator)
  2. 65816: Add 1 cycle if low byte of Direct Page register is not 0

7 - STZ

Store Zero to Memory

Stores zero to memory.

On all processors, the data written to memory is 8-bit. However, for 16-bit processors with the m flag is clear then the data written is 16-bit with the low-order 8-bits at the effective address and the high-order 8-bits at the effective address plus one.

Flags Affected
None.
Instructions
SyntaxOpcode Available on: # of # of Addressing Mode
(hex) 6502 65C02 65816 bytes cycles
STZ addr9C x x 3 41 Absolute
STZ dp64 x x 2 31, 2 Direct Page
STZ addr,X9E x x 3 51 Absolute Indexed X
STZ dp,X74 x x 2 41, 2 Direct Page Indexed X

Notes:

  1. 65816: Add 1 cycle if m=0 (16-bit memory/accumulator)
  2. 65816: Add 1 cycle if low byte of Direct Page register is not 0

8 - Transfer

Transfer data between registers

The transfer register set of instructions allows for data to be passed between different registers.

In all of these transfer instructions, the source register is unchanged.

For example, on the 6502 to save the X register on the stack you would need to use the following:

1TXA      ; Transfer X into A
2PHA      ; Push A to the stack

Note: On the 65C02 and later this is replaced by the PHX instruction which doesn't touch the accumulator.

TAX - Transfer Accumulator to Index Register X

Transfers the Accumulator to X. On the 8-bit processors the registers are all the same size, however on the 16-bit processors the registers can be of different sizes. The following table describes how the data is transferred when a size mismatch occurs:

Source Size Dest Size m x Action performed
8 8 All types Value transferred is 8-bit
8 16 1 0 Value transferred is 16-bit.
The 8-bit A becomes the low byte of the index register.
The 8-bit hidden B register becomes the high byte of the index register.
16 8 0 1 The low byte of A is transferred to the index register
16 16 0 0 The full 16-bit A is transferred to the index register

TAY - Transfer Accumulator to Index Register Y

Transfers the Accumulator to Y. It follows the same rules as TAX.

TCD - Transfer 16-bit accumulator to Direct Page Register

TCD transfers the 16-bit accumulator C to the direct page register D, regardless of the accumulator/memory flag.

The C accumulator is used to indicate that 16-bits are transferred regardless of the m flag. If the A accumulator is 8-bit due to m=1 or in 6502 emulation mode then C = A as the low 8-bits and the hidden B accumulator as the high 8-bits.

TCS - Transfer Accumulator to Stack Pointer

TCS transfers the 16-bit accumulator C to the stack pointer S, regardless of the accumulator/memory flag. The C register is defined above for TCD. An alternate mnemonic for TCS is TAS.

Note: Unlike most transfer instructions, TCS does not affect any flags.

TDC - Transfer Direct Page Register tp 16-bit Accumulator

TDC transfers the Direct Page Register to the 16-bit accumulator C. The C register is defined above for TCD. An alternate mnemonic for TDC is TDA.

TSC - Transfer Stack Pointer to Accumulator

TSC transfers the stack pointer S to the 16-bit accumulator C, regardless of the accumulator/memory flag. The C register is defined above for TCD. An alternate mnemonic for TCS is TSA.

TSX - Transfer Stack Pointer to Index Register X

TSX transfers the stack pointer to X. The stack pointer is unchanged. On 8-bit processors only the low byte is transferred to X. On 16-bit processors (x=0) the full 16-bit value is tranferred to X.

TXA - Transfer Index Register X to Accumulator

TXA transfers X into the accumulator. On the 8-bit processors the registers are all the same size, however on the 16-bit processors the registers can be of different sizes. The following table describes how the data is transferred when a size mismatch occurs:

Source Size Dest Size m x Action performed
8 8 All types Value transferred is 8-bit
8 16 1 0 Value transferred is 16-bit.
The 8-bit index register becomes the low byte of the accumulator.
The high-byte of the accumulator is set to 0.
16 8 0 1 Value transferred is 8-bit.
The low 8-bits of the index register becomes the low byte of the accumulator.
The high-byte of the hidden accumulator B is not affected by the transfer.
16 16 0 0 The full 16-bit index register is transferred to the accumulator

TXS - Transfer Index Register X to the Stack Pointer

TXS transfers X to the stack pointer to. The X is unchanged. On 8-bit processors only the low byte is transferred to S. On 16-bit processors (x=1) the low 8-bits of X is transferred to S. The high 8-bits of S are zeroed. On 16-bit processors (x=0) the full 16-bit value of X is transferred to S.

Note: Unlike most transfer instructions, TXS does not affect any flags.

TXY - Transfer index register X to Y

TXY transfers X to Y. X is unchanged. The registers are always the same size, so when 8-bit then that's what's transferred. When 16-bit (x=0) then 16-bits are transferred.

TYA - Transfer Index Register Y to Accumulator

TYA transfers Y into the accumulator. It follows the same rules as TXA above.

TYX - Transfer index register Y to X

TYX transfers Y to X. Y is unchanged. The registers are always the same size, so when 8-bit then that's what's transferred. When 16-bit (x=0) then 16-bits are transferred.

XBA - Exchange the B & A accumulators

On the 16-bit processors the 16-bit C accumulator is formed of two 8-bit accumulators, A for the low 8-bits and B for the upper 8-bits. XBA swaps the contents of the A & B registers.

In 8-bit memory mode, B is usually referred to as the hidden B accumulator, so the XBA instruction can be used to swap the accessible A with B, providing an in-processor scratch accumulator rather than pushing a value to the stack.

The flags are based on the value of the 8-bit A accumulator

Flags Affected
Flags
n-----z-
nSet if most significant bit of the transferred value is set
zSet if value transferred is zero
Instructions
SrcDestSyntaxOpcode Available on: # of # of Addressing ModeNotes
(hex) 6502 65C02 65816 bytes cycles
A X TAX AA x x x 1 2 Implied
A Y TAY A8 x x x 1 2 Implied
C D TCD 5B x 1 2 Implied
C S TCS 1B x 1 2 Implied Flags are unaffected
D C TDC 7B x 1 2 Implied
S C TSC 3B x 1 2 Implied
S X TSX BA x x x 1 2 Implied
X A TXA 8A x x x 1 2 Implied
X S TXS 9A x x x 1 2 Implied Flags are unaffected
X Y TXY 9B x 1 2 Implied
Y A TYA 98 x x x 1 2 Implied
Y X TYX BB x 1 2 Implied
B A XBA EB x 1 2 Implied Exchanges both registers, flags based on A post exchange