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68000 Microprocessor Family

Notes about assembly language

CC BY-SA

Peter Mount, Area51.dev & Contributors

68000 Microprocessor Family

Notes about assembly language

Title	68000 Microprocessor Family
Subtitle	Notes about assembly language
Author	Peter Mount, Area51.dev & Contributors
Copyright	CC BY-SA

CC BY-SA version 4.0 license

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1 Opcodes

1.1 Conventions

1.2 Arithmetic

1.2.1 ABCD Add Decimal with Extend

1.2.2 ADD

1.2.3 ADDX

2 reference

2.1 Instruction List by Opcode

2.2 Instruction List by Operation

This section covers assembly language for the 68000 Microprocessor family.

This is a work in progress so is definitely incomplete.

Currently, the look and feel is being worked on, as is any backend code required to support this section.

Once that is complete then work can begin to complete the section.

1 - Opcodes

Instruction Set

In this section we cover every available instruction for the 68000 family of processors.

This is a work in progress so is definitely incomplete.

Currently, the look and feel is being worked on, as is any backend code required to support this section.

Once that is complete then work can begin to complete the section.

1.1 - Conventions

The conventions used in the documentation

Operands
An	Any Address Register n (example: A3 is address register 3)
Dn	Any Data Register n (example: D5 is data register 5)
Rn	Any data or address registerData register D7–D0, used during compare.
PC	Program counter
SR	Status register
CCR	Condition codes register (low order byte of SR)
SSP	Supervisor stack pointer
USP	User stack pointer
SP	Active stack pointer (same as A7)
X	Extend flag of the CCR
N	Negative flag of the CCR
Z	Zero flag of the CCR
V	Overflow flag of the CCR
C	Carry flag of the CCR
Immediate data	Immediate data for the instruction
d	Address displacement
Source	Destination Source
contents	Destination contents
Vector	Location of exception vector
ea	Any valid effective address
Notation
+	Arithmetic addition or postincrement indicator
–	Arithmetic subtraction or predecrement indicator
×	Arithmetic multiplication
÷	Arithmetic division or conjunction symbol
~	Invert; operand is logically complemented.
Λ	Logical AND
V	Logical OR
⊕	Logical exclusive OR
→	Source operand is moved to destination operand.
←→	Two operands are exchanged.

1.2 - Arithmetic

Arithmetic operations

1.2.1 - ABCD Add Decimal with Extend

ABCD Add Decimal with Extend

Adds the source operand to the destination operand along with the extend bit, and stores the result in the destination location. The addition is performed using binary-coded decimal arithmetic. The operands, which are packed binary-coded decimal numbers, can be addressed in two different ways:

Data Register to Data Register: The operands are contained in the data registers specified in the instruction
Memory to Memory: The operands are addressed with the predecrement addressing mode using the address registers specified in the instruction.

This operation is a byte operation only.

Operation:

ABCD

Syntax:

ABCD Dy, Dx

ABCD -(Ay), -(Ax)

Data Size:

Byte

Flags:

X	N	Z	V	C
*	U	*	U	*

X Set the same as the carry bit

N Undefined

Z Cleared if the result is nonzero; unchanged otherwise

V Undefined

C Set if a decimal carry was generated; cleared otherwise

Normally, the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations.

Format:

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	Rx			1	0	0	0	0	R/M	Ry
1	1	0	0	Rx			1	0	0	0	0	R/M	Ry

Rx the source register.

Ry the destination register.

R/M Specifies the operand addressing mode:

R/M	Operation
0	Uses data registers
1	Uses address registers or memory

1.2.2 - ADD

Adds the source operand to the destination operand using binary addition and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The mode of the instruction indicates which operand is the source and which is the destination, as well as the operand size.

Operation:

ADD

Syntax:

ADD ea, Dn

ADD Dn, ea

Data Size:

Byte

Word

Long

Flags:

X	N	Z	V	C
*	*	*	*	*

X Set the same as the carry bit

N Set if the result is negative; cleared otherwise

Z Cleared if the result is nonzero; set if zero

V Set if an overflow occurs; cleared otherwise

C Set if a carry is generated; cleared otherwise

Format:

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	Register			Op Mode			Effective Address
1	1	0	1	Register			Dir	Size		Mode			Register

Op Mode:

Dir	Operation
0	\( ea + D_n \longrightarrow D_n \)
1	\( D_n + ea \longrightarrow ea \)

Size	Operation
00	Byte
01	Word
10	Long

Op Mode

Dir	Operation	Size
0	\( ea + D_n \longrightarrow D_n \)	00	Byte
1	\( D_n + ea \longrightarrow ea \)	01	Word
		10	Long

Effective Address— Determines the addressing mode

If the location specified is a source operand, all addressing modes can be used as listed in the following table:

Addressing Mode	Mode	Register	Addressing Mode	Mode	Register
D_n	000	D_n	(xxx).W	111	000
A_n ^[1]	001	A_n	(xxx).L	111	001
(A_n)	010	A_n	#<data>	111	100
(A_n)+	011	A_n
-(A_n)	100	A_n
(D₁₆,A_n)	101	A_n	(D₁₆,PC)	111	010
(D₈,A_n,X_n)	110	A_n	(D₈,PC,X_n)	111	011

Word and long only

If the location specified is a destination operand, only memory alterable addressing modes can be used as listed in the following table:

Addressing Mode	Mode	Register	Addressing Mode	Mode	Register
D_n	‐	‐	(xxx).W	111	000
A_n	‐	‐	(xxx).L	111	001
(A_n)	010	A_n	#<data>	‐	‐
(A_n)+	011	A_n
-(A_n)	100	A_n
(D₁₆,A_n)	101	A_n	(D₁₆,PC)	‐	‐
(D₈,A_n,X_n)	110	A_n	(D₈,PC,X_n)	‐	‐

Note

The D_n mode is used when the destination is a data register.
The destination ea is invalid for a data register.
ADDA is used when the destination is an address register.
ADDI and ADDQ are used when the source is immediate data.
Most assemblers handle the distinction between ADD, ADDI and ADDQ

1.2.3 - ADDX

ADD Extended

Adds the source operand and the extend bit to the destination operand and stores the result in the destination location. The operands can be addressed in two different ways:

Data register to data register: The data registers specified in the instruction contain the operands.
Memory to memory: The address registers specified in the instruction address the operands using the predecrement addressing mode.

The size of the operation can be specified as byte, word, or long.

Operation:

ADDX

Syntax:

ADDX Dy, Dx

ADDX -(Ay), -(Ax)

Data Size:

Byte

Word

Long

Flags:

X	N	Z	V	C
*	*	*	*	*

X Set the same as the carry bit

N Set if the result is negative; cleared otherwise

Z Cleared if the result is nonzero; unchanged otherwise

V Set if an overflow occurs; cleared otherwise

C Set if a carry is generated; cleared otherwise

Normally, the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations.

Format:

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	Rx			1	Size		0	0	R/M	Ry
1	1	0	1	Rx			1	Size		0	0	R/M	Ry

Rx the source register.

Ry the destination register.

R/M Specifies the operand addressing mode:

R/M	Operation
0	Uses data registers
1	Uses address registers or memory

Size the size of the operation:

Size	Operation
00	Byte
01	Word
10	Long

2 - reference

2.1 - Instruction List by Opcode

ABCD	1100XXX10000XXXX
ADD	1101XXXXXXXXXXXX
ADDX	1101XXX1XX00XXXX

2.2 - Instruction List by Operation

Operation	Opcode
ABCD	1100XXX10000XXXX
ADD	1101XXXXXXXXXXXX
ADDX	1101XXX1XX00XXXX

68000 Microprocessor Family

68000 Microprocessor Family

CC BY-SA version 4.0 license

You are free to:

Under the following terms:

Notices:

Table of Contents

1 - Opcodes

1.1 - Conventions

1.2 - Arithmetic

1.2.1 - ABCD Add Decimal with Extend

1.2.2 - ADD

1.2.3 - ADDX

2 - reference

2.1 - Instruction List by Opcode

2.2 - Instruction List by Operation