This the multi-page printable view of this section.Click here to print.

Return to the regular view of this page.

Z80 Assembly Language

Notes about assembly language on the Z80

CC BY-SA

Peter Mount, Area51.dev & Contributors

Z80 Assembly Language

Notes about assembly language on the Z80

TitleZ80 Assembly Language
SubtitleNotes about assembly language on the Z80
AuthorPeter Mount, Area51.dev & Contributors
CopyrightCC BY-SA

CC BY-SA version 4.0 license

You are free to:

  1. Share — copy and redistribute the material in any medium or format
  2. Adapt — remix, transform, and build upon the material or any purpose, even commercially.

This license is acceptable for Free Cultural Works.

The licensor cannot revoke these freedoms as long as you follow the license terms.

Under the following terms:

  1. Attribution — You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
  2. ShareAlike — If you remix, transform, or build upon the material, you must distribute your contributions under the same license as the original.
  3. No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.

Notices:

You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation.

No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.

You can read the full license here: https://creativecommons.org/licenses/by-sa/4.0/

Table of Contents

This section covers assembly language for the Z80 Microprocessor used on machines like the ZX Spectrum, Amstrad CPC and CP/M based machines.

1 - About the Z80

About the Z80

The Z80 is an 8-bit microprocessor introduced by Zilog as the startup company's first product. The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his 11 employees starting in early 1975. The first working samples were delivered in March 1976, and it was officially introduced on the market in July 1976. With the revenue from the Z80, the company built its own chip factories and grew to over a thousand employees over the following two years.

The Zilog Z80 is a software-compatible extension and enhancement of the Intel 8080 and, like it, was mainly aimed at embedded systems. Although used in that role, the Z80 also became one of the most widely used CPUs in desktop computers and home computers from the 1970s to the mid-1980s. It was also common in military applications, musical equipment such as synthesizers (like the Roland Jupiter-8), and coin operated arcade games of the late 1970s and early 1980s including Pac-Man.

1.1 - Z80 Registers

About the Registers available on the Z80

The Z80 contains 208 bits of memory that are available to the programmer as registers.

Z80 Registers
Register Set Special Purpose Registers
Main Alternate
Accumulator Flags Accumulator Flags Interrupt Vector Memory Refresh
A F A' F' I R
B C B' C' Index Register IX Index Register IY
D E D' E' Stack Pointer SP
H H H' L' Program Counter PC

Accumulator and Flag registers

The Z80 provides two independent 8-bit accumulators each with an associated flag register. The programmer can switch between the two pairs with the EX AF, AF' instruction.

General Purpose registers

Two matched sets of general purpose registers are available, each set containing six 8-bit registers: B, C, D, E, H and L.

These registers are also arranged to provide 3 16-bit registers: BC, DE and HL.

The HL register pair is usually used for addressing memory and has more instructions available to it for this purpose than BC or DE register pairs.

The programmer can switch between the main (BC, DE and HL) and alternate (BC', DE' and HL') set of general purpose registers with the EXX instruction.

PC Program Counter

The program counter holds the 16-bit address of the current instruction being fetched from memory. The Program Counter is automatically incremented after its contents are transferred to the address lines. When a program jump occurs, the new value is automatically placed in the Program Counter, overriding the incrementer.

SP Stack Pointer

The stack pointer holds the 16-bit address of the current top of a stack located anywhere in external system RAM. The external stack memory is organized as a last-in first-out (LIFO) file. Data can be pushed onto the stack using the PUSH instructions or popped off of the stack using the POP instructions.

1.2 - Z80 Status Flags

The Flag registers, F and F', supply information to the user about the status of the Z80 CPU at any particular time. Each of these two Flag registers contains 6 bits of status information that are set or cleared by CPU operations; bits 3 and 5 are not used.

Four of these bits (C, P/V, Z, and S) can be tested for use with conditional JUMP, CALL, or RETURN instructions.

The H and N flags cannot be tested; these two flags are used for BCD arithmetic.

7 6 5 4 3 2 1 0
S Z H P/V N C

C Carry

The Carry Flag (C) is set or cleared depending on the operation being performed.

For ADD instructions that generate a Carry, and for SUB instructions that generate a Borrow, the Carry Flag is set.

The Carry Flag is reset by an ADD instruction that does not generate a Carry, and by a SUB instruction that does not generate a Borrow.

This saved Carry facilitates software routines for extended precision arithmetic.

Additionally, the DAA instruction sets the Carry Flag if the conditions for making the decimal adjustment are met.

For the RLA, RRA, RLS, and RRS instructions, the Carry bit is used as a link between the least-significant byte (LSB) and the most-significant byte (MSB) for any register or memory location. During the RLCA, RLC, and SLA instructions, the Carry flag contains the final value shifted out of bit 7 of any register or memory location. During the RRCA, RRC, SRA, and SRL instructions, the Carry flag contains the final value shifted out of bit 0 of any register or memory location.

For the logical instructions AND, OR, and XOR, the Carry flag is reset.

The Carry flag can also be set by the Set Carry Flag (SCF) instruction and complemented by the Compliment Carry Flag (CCF) instruction.

Z Zero

The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the execution of certain instructions is 0.

For 8-bit arithmetic and logical operations, the Z flag is set to a 1 if the resulting byte in the Accumulator is 0. If the byte is not 0, the Z flag is reset to 0.

For Compare (search) instructions, the Z flag is set to 1 if the value in the Accumulator is equal to the value in the memory location indicated by the value of the register pair HL.

When testing a bit in a register or memory location, the Z flag contains the complemented state of the indicated bit.

When inputting or outputting a byte between a memory location and an INI, IND, OUTI, or OUTD I/O device, if the result of decrementing Register B is 0, then the Z flag is 1; otherwise, the Z flag is 0. Additionally, for byte inputs from I/O devices using IN r, (C), the Z flag is set to indicate a 0-byte input.

P/V Parity Overflow

The Parity/Overflow (P/V) Flag is set to a specific state depending on the operation being performed.

Overflow

For arithmetic operations, this flag indicates an overflow condition when the result in the Accumulator is greater than the maximum possible number (+127) or is less than the minimum possible number (–128). This overflow condition is determined by examining the sign bits of the operands.

For addition, operands with different signs never cause overflow. When adding operands with similar signs and the result contains a different sign, the Overflow Flag is set.

For subtraction, overflow can occur for operands of unalike signs. Operands of alike signs never cause overflow.

Another method for identifying an overflow is to observe the Carry to and out of the sign bit. If there is a Carry in and no Carry out, or if there is no Carry in and a Carry out, then an Overflow has occurred.

Parity

This flag is also used with logical operations and rotate instructions to indicate the resulting parity is even. The number of 1 bits in a byte are counted. If the total is Odd, ODD parity is flagged (i.e., P = 0). If the total is even, even parity is flagged (i.e., P = 1).

When inputting a byte from an I/O device with an IN r, (C) instruction, the P/V Flag is adjusted to indicate data parity.

Alternate usage

During the CPI, CPIR, CPD, and CPDR search instructions and the LDI, LDIR, LDD, and LDDR block transfer instructions, the P/V Flag monitors the state of the Byte Count (BC) Register. When decrementing, if the byte counter decrements to 0, the flag is cleared to 0; otherwise the flag is set to 1.

During the LD A, I and LD A, R instructions, the P/V Flag is set with the value of the interrupt enable flip-flop (IFF2) for storage or testing.

S Sign

The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7). When the Z80 CPU performs arithmetic operations on signed numbers, the binary twos-complement notation is used to represent and process numeric information.

A positive number is identified by a 0 in Bit 7. A negative number is identified by a 1.

The binary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0 to 127.

A negative number is represented by the twos complement of the equivalent positive number. The total range for negative numbers is from –1 to –128.

When inputting a byte from an I/O device to a register using an IN r, (C) instruction, the S Flag indicates either positive (S = 0) or negative (S = 1) data.

N Add/Subtract

The Add/Subtract Flag (N) is used by the Decimal Adjust Accumulator instruction (DAA) to distinguish between the ADD and SUB instructions.

For ADD instructions, N is cleared to 0. For SUB instructions, N is set to 1.

H Half Carry

The Half Carry Flag (H) is set (1) or cleared (0) depending on the Carry and Borrow status between bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the Decimal Adjust Accumulator (DAA) instruction to correct the result of a packed BCD add or subtract operation.

For ADD instructions, H is set if a carry occurs from bit 3 to bit 4. For SUB instructions, H is set if a borrow from bit 4 occurs.

1.3 - Addresses

The addresses used ny the Z80

The Z80 uses a fixed set of addresses in Page 0 of the address space:

Address Instruction Usage
0000 RST 0 Initial power on
RST 0 instruction is invoked.
RESET pin is held low
0008 RST 1 RST 1 instruction is invoked.
0010 RST 2 RST 2 instruction is invoked.
0018 RST 3 RST 3 instruction is invoked.
0020 RST 4 RST 4 instruction is invoked.
0028 RST 5 RST 5 instruction is invoked.
0030 RST 6 RST 6 instruction is invoked.
0038 RST 7 RST 7 instruction is invoked.
INT Maskable Interrupt handler when in Interrupt Mode 1
0066 NMI interrupt handler

Addresses 0x0000…0x003F are used by the 8 RST instructions with 8 bytes available for each. RST 0 is also the start address for when the processor powers on or is reset.

1.4 - Pin Layout

The physical Z80 processor

General pins

A0…A15 Address Bus

Address Bus (output, active High, tristate). A0…A15 form a 16-bit Address Bus, which provides the addresses for memory data bus exchanges (up to 64 KB) and for I/O device exchanges.

D0…D7 Data Bus

D0…D7 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.

CLK Clock (input)

Single-phase MOS-level clock.

System Control

M1 Machine Cycle One (output, active Low)

M1, together with MREQ, indicates that the current machine cycle is the op code fetch cycle of an instruction execution. M1, when operating together with IORQ, indicates an interrupt acknowledge cycle.

MREQ Memory Request (output, active Low, tristate)

MREQ indicates that the address bus holds a valid address for a memory read or a memory write operation.

IORQ Input/Output Request (output, active Low, tristate)

IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.

RD Read (output, active Low, tristate)

RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.

WR Write (output, active Low, tristate)

WR indicates that the CPU data bus contains valid data to be stored at the addressed memory or I/O location.

RFSH Refresh (output, active Low)

RFSH, together with MREQ, indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.

Bus Control

BUSACK Bus Acknowledge

The BUSACK pin indicates to the requesting device that the CPU address bus, data bus and control signals MREQ, IORQ, RD and WR have entered their high-impedance states and other devices on the bus can control those lines.

BUSREQ Bus Request

BUSREQ contains a higher priority than NMI and is always recognized at the end of the current machine cycle.

BUSREQ forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD and WR to enter a high-impedance state so that other devices can control these lines. BUSREQ is normally wired OR and requires an external pull-up for these applications.

Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAM.

CPU Control

HALT HALT State (output, active Low)

HALT indicates that the CPU has executed a HALT instruction and is waiting for either a nonmaskable or a maskable interrupt (with the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to maintain memory refreshes.

WAIT WAIT (input, active Low)

WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.

INT Interrupt Request (input, active Low)

An Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and requires an external pull-up for these applications.

NMI Nonmaskable Interrupt (input, negative edge-triggered)

NMI contains a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066h.

RESET Reset (input, active Low)

RESET initializes the CPU as follows:

  • it resets the interrupt enable flip-flop,
  • clears the Program Counter and registers I and R,
  • sets the interrupt status to Mode 0.

During reset time, the address and data bus enter a high-impedance state, and all control output signals enter an inactive state. RESET must be active for a minimum of three full clock cycles before a reset operation is complete.

2 - Timing

How the system clock relates to processor speed

The Z80 processor executes instructions as a series of basic operations:

Each of these operations is known as a Machine cycle (M-cycle), which can take between 3 and 6 T-Cycles to execute, although this can be extended by the WAIT signal. A T-cycle (Time Cycle) is one cycle of the system clock.

The following diagram shows an example of a single instruction that reads from memory and writes back.

Visualisation of the timing of a single CPU instruction

Opcode fetch

The Opcode fetch takes 4 T-cycles:

Visualisation of the timing of fetching an opcode

T1 Sets the Address bus A0…15 to the current value of the program counter.
T2 Reads the opcode during the second half of the cycle.
T3 and T4 has the refresh address set on the Address Bus. This is to allow dynamic ram to be refreshed.

Memory Access

Memory access cycles are generally three T-cycles long unless wait states are requested by memory via the WAIT signal.

Memory Read Cycle

For a memory read the MREQ and RD signals are pulled low once the address bus is stable.

Visualisation of the timing of reading from memory

Memory Write Cycle

For a memory write the MREQ and WR signals are pulled low once the address bus is stable.

Visualisation of the timing of writing to memory

WR goes inactive half a T-State before the address and data bus contents are changed to support different types of memory.

I/O Cycles

I/O operations are similar to memory, except the IORQ signal is used instead of MREQ to indicate that devices not memory should respond.

Also an additional wait state is inserted after T-State 2. The reason for this single wait state insertion is that during I/O operations, the period from when the IORQ signal goes active until the CPU must sample the WAIT line is short. Without this extra state, sufficient time does not exist for an I/O port to decode its address and activate the WAIT line if a wait is required. Additionally, without this wait state, it is difficult to design MOS I/O devices that can operate at full CPU speed. During this wait state period, the WAIT request signal is sampled.

I/O Read Cycle

During a read I/O operation, the RD line is used to enable the addressed port onto the data bus, just as in the case of a memory read.

Visualisation of the timing of reading from a device

I/O Write Cycle

During a write I/O operation, the WR line is used to enable the addressed port onto the data bus, just as in the case of a memory write.

Visualisation of the timing of writing to a device

3 - Opcodes

Instruction Set

Instruction Notation Summary

Notation Description
r Identifies any of the registers A, B, C, D, E, H or L
(HL) Identifies the contents of the memory location whose address is specified by the contents of the HL register pair.
(IX + d) Identifies the contents of the memory location, whose address is specified by the contents of the Index register pair IX plus the signed displacement d
(IY + d) Identifies the contents of the memory location, whose address is specified by the contents of the Index register pair IY plus the signed displacement d
n Identifies a one-byte unsigned integer expression in the range (0 to 255)
nn Identifies a two-byte unsigned integer expression in the range (0 to 65535) (0x0000 to 0xFFFF)
b Identifies a one-byte signed integer expression in the range (-128 to +127)
e Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location
cc Identifies the status of the Flag Register as any of ( NZ, Z, NC, C, PO, PE, P or M ) for the conditional jumps, calls, and return instructions
qq Identifies any of the register pairs BC, DE, HL or AF
ss Identifies any of the register pairs BC, DE, HL or SP
pp Identifies any of the register pairs BC, DE, IX or SP
rr Identifies any of the register pairs BC, DE, IY or SP
s Identifies any of r, n, (HL), (IX+d) or (IY+d)
m Identifies any of r, (HL), (IX+d) or (IY+d)

3.1 - Load

Load registers, data & memory

3.1.1 - LD (dd), n

Load number into memory
76543210
 
\((HL) \longleftarrow n\)
LD (HL), n
0011011036
n
 
\(( IX + d ) \longleftarrow n\)
LD (IX+d), n
11011101DD
0011011036
d
n
 
\(( IY + d ) \longleftarrow n\)
LD (IY+d), n
11111101FD
0011011036
d
n
Flags Affected
None.
Opcode Matrix
(HL)(IX+d)(IY+d)
n
LD (HL), n
36nn210
LD (IX+d), n
DD36nnnn419
LD (IY+d), n
FD36nnnn419
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Implicit

3.1.2 - LD (dd), s

Store register into memory via register
76543210
 
\((BC) \longleftarrow A\)
LD (BC), A
0000001002
 
\((DE) \longleftarrow A\)
LD (DE), A
0001001012
 
\((HL) \longleftarrow r\)
LD (HL), r
01110r
 
\(( IX + d ) \longleftarrow r\)
LD (IX+d), r
11011101DD
01110r
d
 
\(( IY + d ) \longleftarrow r\)
LD (IY+d), r
11111101FD
01110r
d
 
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
None.
Opcode Matrix
ABCDEHL
(HL)
LD (HL), A
7717
LD (HL), B
7017
LD (HL), C
7117
LD (HL), D
7217
LD (HL), E
7317
LD (HL), H
7417
LD (HL), L
7517
(BC)
LD (BC), A
0217






(DE)
LD (DE), A
1217






(IX+d)
LD (IX+d), A
DD77nn319
LD (IX+d), B
DD70nn319
LD (IX+d), C
DD71nn319
LD (IX+d), D
DD72nn319
LD (IX+d), E
DD73nn319
LD (IX+d), H
DD74nn319
LD (IX+d), L
DD75nn319
(IY+d)
LD (IY+d), A
FD77nn319
LD (IY+d), B
FD70nn319
LD (IY+d), C
FD71nn319
LD (IY+d), D
FD72nn319
LD (IY+d), E
FD73nn319
LD (IY+d), H
FD74nn319
LD (IY+d), L
FD75nn319
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.1.3 - LD (nn), s

Store register into memory via address
76543210
 
\((nn) \longleftarrow A\)
LD (nn), A
0011001032
7nn0
158
 
\((nn+1) \longleftarrow dd_h, (nn) \longleftarrow dd_l\)
LD (nn), dd
11101101ED
01dd0011
7nn0
158
 
\((nn+1) \longleftarrow H, (nn) \longleftarrow L\)
LD (nn), HL
0010001022
7nn0
158
 
\((nn+1) \longleftarrow IX_h, (nn) \longleftarrow IX_l\)
LD (nn), IX
11011101DD
0010001022
7nn0
158
 
\((nn+1) \longleftarrow IY_h, (nn) \longleftarrow IY_l\)
LD (nn), IY
11111101FD
0010001022
7nn0
158
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
ABCDEHLIXIYSP
(nn)
LD (nn), A
32nnnn313


LD (nn), HL
22nnnn316



(nn)

LD (nn), BC
ED43nnnn420
LD (nn), DE
ED53nnnn420
LD (nn), HL
ED63nnnn420
LD (nn), IX
DD22nnnn420
LD (nn), IY
FD22nnnn420
LD (nn), SP
ED73nnnn420
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.1.4 - LD A,I and LDA A,R

8-bit register instructions
76543210
 
\(A \longleftarrow I\)
LD A, I
11101101ED
0101011157
 
\(A \longleftarrow R\)
LD A, R
11101101ED
010111115F
Flags Affected
Flags
sz---p/v--
sSet if the source register is negative
zSet if the source register is 0
p/vContains contents of IFF2,
0 if an interrupt occurs during the instruction running
Opcode Matrix
IR
A
LD A, I
ED5729
LD A, R
ED5F29
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.1.5 - LD dd, nn

Load 16-bit number
76543210
 
\(dd \longleftarrow nn\)
LD dd, nn
00dd0001
7nn0
158
 
\(IX \longleftarrow nn\)
LD IX, nn
11011101DD
0010000121
7nn0
158
 
\(IY \longleftarrow nn\)
LD IY, nn
11111101FD
0010000121
7nn0
158
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
BCDEHLIXIYSP
nn
LD BC, nn
01nnnn310
LD DE, nn
11nnnn310
LD HL, nn
21nnnn310
LD IX, nn
DD21nnnn414
LD IY, nn
FD21nnnn414
LD SP, nn
31nnnn310
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Implicit

3.1.6 - LD r, s

8-bit register instructions
76543210
 
\(r \longleftarrow r'\)
LD r, r'
01rr'
 
\(r \longleftarrow n\)
LD r, n
00r110
n
 
\(A \longleftarrow (BC)\)
LD A, (BC)
000010100A
 
\(A \longleftarrow (DE)\)
LD A, (DE)
000110101A
 
\(r \longleftarrow (HL)\)
LD r, (HL)
01r110
 
\(r \longleftarrow (IX+d)\)
LD r, (IX+d)
11011101DD
01r110
d
 
\(r \longleftarrow (IY+d)\)
LD r, (IY+d)
11111101FD
01r110
d
 
\(I \longleftarrow A\)
 
LD I,A
11101101ED
0100011147
 
\(R \longleftarrow A\)
LD R, A
11101101ED
010011114F
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
None.
Opcode Matrix
ABCDEHL(HL)(BC)(DE)(IX+d)(IY+d)n
A
LD A, A
7F14
LD A, B
7814
LD A, C
7914
LD A, D
7A14
LD A, E
7B14
LD A, H
7C14
LD A, L
7D14
LD A, (HL)
7E17
LD A, (BC)
0A17
LD A, (DE)
1A17
LD A, (IX+d)
DD7Enn319
LD A, (IY+d)
FD7Enn319
LD A, n
3Enn27
B
LD B, A
4714
LD B, B
4014
LD B, C
4114
LD B, D
4214
LD B, E
4314
LD B, H
4414
LD B, L
4514
LD B, (HL)
4617


LD B, (IX+d)
DD46nn319
LD B, (IY+d)
FD46nn319
LD B, n
06nn27
C
LD C, A
4F14
LD C, B
4814
LD C, C
4914
LD C, D
4A14
LD C, E
4B14
LD C, H
4C14
LD C, L
4D14
LD C, (HL)
4E17


LD C, (IX+d)
DD4Enn319
LD C, (IY+d)
FD4Enn319
LD C, n
0Enn27
D
LD D, A
5714
LD D, B
5014
LD D, C
5114
LD D, D
5214
LD D, E
5314
LD D, H
5414
LD D, L
5514
LD D, (HL)
5617


LD D, (IX+d)
DD56nn319
LD D, (IY+d)
FD56nn319
LD D, n
16nn27
E
LD E, A
5F14
LD E, B
5814
LD E, C
5914
LD E, D
5A14
LD E, E
5B14
LD E, H
5C14
LD E, L
5D14
LD E, (HL)
5E17


LD E, (IX+d)
DD5Enn319
LD E, (IY+d)
FD5Enn319
LD E, n
1Enn27
H
LD H, A
6714
LD H, B
6014
LD H, C
6114
LD H, D
6214
LD H, E
6314
LD H, H
6414
LD H, L
6514
LD H, (HL)
6617


LD H, (IX+d)
DD66nn319
LD H, (IY+d)
FD66nn319
LD H, n
26nn27
L
LD L, A
6F14
LD L, B
6814
LD L, C
6914
LD L, D
6A14
LD L, E
6B14
LD L, H
6C14
LD L, L
6D14
LD L, (HL)
6E17


LD L, (IX+d)
DD6Enn319
LD L, (IY+d)
FD6Enn319
LD L, n
2Enn27
I
LD I, A
ED4724












R
LD R, A
ED4F24












Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit Special

3.1.7 - LD s, (nn)

Load register from memory
76543210
 
\(A \longleftarrow (nn)\)
LD A, (nn)
001110103A
7nn0
158
 
\(H \longleftarrow (nn+1), L \longleftarrow (nn)\)
LD HL, (nn)
001010102A
7nn0
158
 
\(dd_h \longleftarrow (nn+1), dd_l \longleftarrow (nn)\)
LD dd, (nn)
11101101ED
01dd1011
7nn0
158
 
\(IX_h \longleftarrow (nn+1), IX_l \longleftarrow (nn)\)
LD IX, (nn)
11011101DD
001010102A
7nn0
158
 
\(IY_h \longleftarrow (nn+1), IY_l \longleftarrow (nn)\)
LD IY, (nn)
11111101FD
001010102A
7nn0
158
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
ABCDEHLIXIYSP
(nn)
LD A, (nn)
3Annnn313


LD HL, (nn)
2Annnn316



(nn)

LD BC, (nn)
ED4Bnnnn420
LD DE, (nn)
ED5Bnnnn420
LD HL, (nn)
ED6Bnnnn420
LD IX, (nn)
DD2Annnn420
LD IY, (nn)
FD2Annnn420
LD SP, (nn)
ED7Bnnnn420
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.1.8 - LD SP, s

Set Stack Pointer from register
76543210
 
\(SP \longleftarrow HL\)
LD SP,HL
11111001F9
 
\(SP \longleftarrow IX\)
LD SP, IX
11011101DD
11111001F9
 
\(SP \longleftarrow IY\)
LD SP, IY
11111101FD
11111001F9
Flags Affected
None.
Opcode Matrix
HLIXIY
SP
LD SP, HL
F916
LD SP, IX
DDF926
LD SP, IY
FDF926
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.2 - Arithmetic

Arithmetic

3.2.1 - ADD without carry

Addition without carry

The ADD instruction performs an addition without carry. Any overflow from the addition will be passed on to the carry flag.

3.2.1.1 - ADD r without carry

Addition of a register without carry
76543210
 
\(A \longleftarrow A + r\)
ADD A, r
10000r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h----
sset if result negative
zset if result is 0
hset if carry from bit 3
Opcode Matrix
ABCDEHL
A
ADD A,A
8714
ADD A,B
8014
ADD A,C
8114
ADD A,D
8214
ADD A,E
8314
ADD A,H
8414
ADD A,L
8514
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.2.1.2 - ADD n without carry

Addition of a number without carry
76543210
 
\(A \longleftarrow A + n\)
ADD A, n
11000110C6
n
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if overflow
cset if carry from bit 7
Opcode Matrix
n
A
ADD A,n
C6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Implicit

3.2.1.3 - ADD (dd) without carry

Addition of memory without carry
76543210
 
\(A \longleftarrow A + (HL)\)
ADD A, (HL)
1000011086
 
\(A \longleftarrow A + (IX+d)\)
ADD A, (IX+d)
11011101DD
1000011086
d
 
\(A \longleftarrow A + (IY+d)\)
ADD A, (IY+d)
11111101FD
1000011086
d
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if overflow
cset if carry from bit 7
Opcode Matrix
(HL)(IX+d)(IY+d)
A
ADD A,(HL)
8617
ADD A,(IX+d)
DD86nn319
ADD A,(IY+d)
FD86nn319
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.2.1.4 - ADD ss to HL without carry

Addition without carry
76543210
 
\(HL \longleftarrow HL + dd\)
ADD HL, dd
00dd1001
 
\(IX \longleftarrow IX + pp\)
ADD IX, pp
11011101DD
00pp1001
 
\(IY \longleftarrow IY + mm\)
ADD IY, mm
11111101FD
00mm1001
Registers
Valueddmmpp
00BCBCBC
01DEDEDE
10HLIYIX
11SPSPSP
Flags Affected
Flags
sz-h---c
sset if result negative
zset if result is 0
hset if carry from bit 11
cset if carry from bit 15
Opcode Matrix
BCDEHLSPIXIY
HL
ADD HL,BC
09111
ADD HL,DE
19111
ADD HL,HL
29111
ADD HL,SP
39111


IX
ADD IX,BC
DD09215
ADD IX,DE
DD19215

ADD IX,SP
DD39215
ADD IX,IX
DD29215

IY
ADD IY,BC
FD09215
ADD IY,DE
FD19215

ADD IY,SP
FD39215

ADD IY,IY
FD29215
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.2.2 - ADC Add with Carry

Addition with carry

The ADC instruction performs an addition with carry. If carry is set then it will be included in the calculation whilst any overflow from the addition will be passed on to the carry flag.

3.2.2.1 - ADC 8 bit add with Carry

Addition with carry
76543210
 
\(A \longleftarrow A + r + Carry\)
ADC A,r
10001r
 
\(A \longleftarrow A + n + Carry\)
ADC A,n
11001110CE
n
 
\(A \longleftarrow A + (HL) + Carry\)
ADC A, (HL)
100011108E
 
\(A \longleftarrow A + (IX+d) + Carry\)
ADC A, (IX + d)
11011101DD
100011108E
d
 
\(A \longleftarrow A + (IY+d) + Carry\)
ADC A, (IY + d)
11111101FD
100011108E
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if overflow
cset if carry from bit 7
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
ADC A,A
8F14
ADC A,B
8814
ADC A,C
8914
ADC A,D
8A14
ADC A,E
8B14
ADC A,H
8C14
ADC A,L
8D14
ADC A,(HL)
8E17
ADC A,(IX+d)
DD8Enn319
ADC A,(IY+d)
FD8Enn319
ADC A,n
CEnn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3.2.2.2 - ADC 16 bit add with Carry

Addition with carry
76543210
 
\(HL \longleftarrow HL + ss + Carry\)
ADC HL, dd
11101101ED
01dd1010
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 11
p/vset if overflow
cset if carry from bit 15
Opcode Matrix
BCDEHLSP
HL
ADC HL,BC
ED4A215
ADC HL,DE
ED5A215
ADC HL,HL
ED6A215
ADC HL,SP
ED7A215
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.2.3 - SUB Subtract without Carry

Subtraction without Carry

\(A \longleftarrow A - s\)

This s operand is any of r, n, (HL), (IX+d), or (IY+d).

These possible op code/operand combinations are assembled as follows in the object code:

76543210
 
SUB r
10010r
 
SUB n
11010110D6
n
 
SUB (HL)
1001011096
 
SUB (IX+d)
11011101DD
1001011096
d
 
SUB (IX+d)
11111101FD
1001011096
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if overflow
cset if borrow
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
SUB A,A
9714
SUB A,B
9014
SUB A,C
9114
SUB A,D
9214
SUB A,E
9314
SUB A,H
9414
SUB A,L
9514
SUB A,(HL)
9617
SUB A,(IX+d)
DD96nn319
SUB A,(IY+d)
FD96nn319
SUB A,n
D6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3.2.4 - SBC Subtract with Carry

Subtraction with Carry
76543210
 
\(A \longleftarrow A - r - Carry\)
SBC A, r
10011r
 
\(A \longleftarrow A - n - Carry\)
SBC A,n
11011110DE
 
\(A \longleftarrow A - (HL) - Carry\)
SBC A, (HL)
100111109E
 
\(A \longleftarrow A - (IX+d) - Carry\)
SBC A, (IX+d)
11011101DD
100111109E
d
 
\(A \longleftarrow A - (IY+d) - Carry\)
SBC A, (IY+d)
11111101FD
100111109E
d
 
\(A \longleftarrow A - ss - Carry\)
SBC HL, ss
11101101ED
01dd0010
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if overflow
cset if borrow
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)nBCDEHLSP
A
SBC A,A
9F14
SBC A,B
9814
SBC A,C
9914
SBC A,D
9A14
SBC A,E
9B14
SBC A,H
9C14
SBC A,L
9D14
SBC A,(HL)
9E17
SBC A,(IX+d)
DD9Enn119
SBC A,(IY+d)
FD9Enn119
SBC A,n
DEnn27




HL











SBC HL,BC
ED42215
SBC HL,DE
ED52215
SBC HL,HL
ED62215
SBC HL,SP
ED72215
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3.2.5 - AND

Binary AND

\(A \longleftarrow A \land s\)

76543210
 
AND r
10100r
 
AND n
11100110E6
n
 
AND(HL)
10100110A6
 
AND (IX+d)
11011101DD
10100110A6
d
 
AND (IY+d)
11111101FD
10100110A6
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset
p/vset if overflow
creset
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
AND A,A
A714
AND A,B
A014
AND A,C
A114
AND A,D
A214
AND A,E
A314
AND A,H
A414
AND A,L
A514
AND A,(HL)
A617
AND A,(IX+d)
DDA6nn319
AND A,(IY+d)
FDA6nn319
AND A,n
E6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3.2.6 - OR

Binary OR

\(A \longleftarrow A \lor s\)

76543210
 
OR r
10110r
 
OR n
11110110F6
n
 
OR (HL)
10110110B6
 
OR (IX+d)
11011101DD
10110110B6
d
 
OR (IY+d)
11111101FD
10110110B6
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if overflow
creset
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
OR A,A
B714
OR A,B
B014
OR A,C
B114
OR A,D
B214
OR A,E
B314
OR A,H
B414
OR A,L
B514
OR A,(HL)
B617
OR A,(IX+d)
DDB6nn319
OR A,(IY+d)
FDB6nn319
OR A,n
F6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3.2.7 - XOR

Binary Exclusive OR

\(A \longleftarrow A \oplus s\)

76543210
 
XOR r
10101r
 
XOR n
11101110EE
n
 
XOR (HL)
10101110AE
 
XOR (IX+d)
11011101DD
10101110AE
d
 
XOR (IY+d)
11111101FD
10101110AE
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if overflow
creset
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
XOR A,A
AF14
XOR A,B
A814
XOR A,C
A914
XOR A,D
AA14
XOR A,E
AB14
XOR A,H
AC14
XOR A,L
AD14
XOR A,(HL)
AE17
XOR A,(IX+d)
DDAEnn319
XOR A,(IY+d)
FDAEnn319
XOR A,n
EEnn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3.2.8 - INC Increment

Increment by 1

INC increments either an 8-bit register or an 16-bit register pair.

3.2.8.1 - INC 8-bit Increment

Increment 8-bit register by 1
76543210
 
\(s \longleftarrow r + 1\)
INC r
00r100
 
\((HL) \longleftarrow (HL) + 1\)
INC (HL)
0011010034
 
\((IX+d) \longleftarrow (IX+d) + 1\)
INC (IX+d)
11011101DD
0011010034
d
 
\((IY+d) \longleftarrow (IY+d) + 1\)
INC (IY+d)
11111101FD
0011010034
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if register was 0x7F before operation, reset otherwise
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
Op
INC A
3C14
INC B
0414
INC C
0C14
INC D
1414
INC E
1C14
INC H
2414
INC L
2C14
INC (HL)
34111
INC (IX+d)
DD34nn323
INC (IY+d)
FD34nn323
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.2.8.2 - INC 16-bit Increment

Increment 16-bit register pair by 1
76543210
 
\(dd \longleftarrow dd + 1\)
INC qq
00dd0011
 
\(IX \longleftarrow IX + 1\)
INC IX
11011101DD
0010001123
 
\(IY \longleftarrow IY + 1\)
INC IY
11111101FD
0010001123
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
BCDEHLSPIXIY
Op
INC BC
0316
INC DE
1316
INC HL
2316
INC SP
3316
INC IX
DD23210
INC IY
FD23210
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.2.9 - DEC Decrement

Decrement

DEC decrements either an 8-bit register or an 16-bit register pair.

3.2.9.1 - DEC 8-bit Decrement

Decrement
76543210
 
\(r \longleftarrow r - 1\)
DEC r
00r101
 
\((HL) \longleftarrow (HL) - 1\)
DEC (HL)
00110101
 
\((IX+d) \longleftarrow (IX+d) - 1\)
DEC (IX+d)
11011101DD
0011010135
d
 
\((IY+d) \longleftarrow (IY+d) - 1\)
DEC (IY+d)
11111101FD
0011010135
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if register was 0x80 before operation, reset otherwise
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
Op
DEC A
3D14
DEC B
0514
DEC C
0D14
DEC D
1514
DEC E
1D14
DEC H
2514
DEC L
2D14
DEC (HL)
35111
DEC (IX+d)
DD35nn323
DEC (IY+d)
FD35nn323
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.2.9.2 - DEC 16-bit Decrement

Decrement 16-bit register pair
76543210
 
\(dd \longleftarrow dd - 1\)
DEC dd
00dd1011
 
\(IX \longleftarrow IX - 1\)
DEC IX
11011101DD
001010112B
 
\(IY \longleftarrow IY - 1\)
DEC IY
11111101FD
001010112B
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
BCDEHLSPIXIY
Op
DEC BC
0B16
DEC DE
1B16
DEC HL
2B16
DEC SP
3B16
DEC IX
DD2B210
DEC IY
FD2B210
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.2.10 - CP

Comparison

\(A - s\)

76543210
 
CP r
10111r
 
CP n
11111110FE
n
 
CP (HL)
10111110BE
 
CP (IX+d)
11011101DD
10111110BE
d
 
CP (IY+d)
11111101FD
10111110BE
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if overflow
cset if borrow
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
Op
CP A
BF14
CP B
B814
CP C
B914
CP D
BA14
CP E
BB14
CP H
BC14
CP L
BD14
CP (HL)
BE17
CP (IX+d)
DDBEnn319
CP (IY+d)
FDBEnn319
CP n
FEnn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3.3 - Program Flow

Jump, Call and Return

3.3.1 - Jump absolute

76543210
 
\(PC \longleftarrow nn\)
JP nn
11000011C3
7nn0
158
 
\(\begin{rcases} PC \longleftarrow nn \end{rcases} \text {if } ccc = true\)
11ccc010
7nn0
158
 
\(PC \longleftarrow HL\)
JP (HL)
11101001E9
 
\(PC \longleftarrow IX\)
JP (IX)
11011101DD
11101001E9
 
\(PC \longleftarrow IY\)
JP (IY)
11111101FD
11101001E9
Conditions
cccAbbrev Condition Flag
000NZ Non Zero Z
001Z Zero
010NC No Carry C
011C Carry
100 PO Parity Odd P/V
101 PE Parity Even
110 P Sign Positive S
111 M Sign Negative

Jumps to 16bit registers

Although the instruction JP (HL) looks like it's using indirect addressing, it doesn't. It takes the address in HL as the new PC, so it should be read as if it's JP HL.

The same applies for JP (IX) and JP (IY) - the actual register is used not the value at that address.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZPEPONP
JP nn
JP nn
C3nnnn310
JP C,nn
DAnnnn310
JP NC,nn
D2nnnn310
JP Z,nn
CAnnnn310
JP NZ,nn
C2nnnn310
JP PE,nn
EAnnnn310
JP PO,nn
E2nnnn310
JP N,nn
FAnnnn310
JP P,nn
F2nnnn310
JP (HL)
JP (HL)
E914








JP (IX)
JP (IX)
DDE928








JP (IY)
JP (IY)
FDE928








Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.3.2 - Jump Relative

76543210
 
\(PC \longleftarrow PC + e\)
JR e
0001100018
e-2
 
\(\begin{rcases} PC \longleftarrow (PC) + e \end{rcases} \text {if } cc = true\)
JR cc, e
001cc000
e-2
 
\(B \longleftarrow B - 1\\ \begin{rcases} PC \longleftarrow PC + e \end{rcases} \text{ if } B \not = 0\)
DJNZ e
0001000010
e-2
Conditions
ccAbbrev Condition Flag
00NZ Non Zero Z
01Z Zero
10NC No Carry C
11C Carry

Relative Jumps

For relative instructions the offset is taken from the address of the op code so is in the range -126 to 129. Assemblers usually account for the difference where the value in memory is e-2.

Timing

For JR then when a jump takes place then it takes 12(4,3,5) T-States whilst no jump 7(4,3) T-States.

For DJNZ if the jump takes place then it takes 13 (5,3,5) T-States. If no jump then 8 (5,3) T-States.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZB!=0
JR e
JR e
18nn212
JR C,e
38nn212
JR NC,e
30nn212
JR Z,e
28nn212
JR NZ,e
20nn212

DJNZ e





DJNZ e
10nn213
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.3.3 - Call subroutine

76543210
 
\((SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn\)
CALL nn
11001101CD
7nn0
158
 
\(\begin{rcases} (SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn \end{rcases} \text{ if } ccc = true\)
CALL ccc, nn
11ccc100CD
7nn0
158
Conditions
cccAbbrev Condition Flag
000NZ Non Zero Z
001Z Zero
010NC No Carry C
011C Carry
100 PO Parity Odd P/V
101 PE Parity Even
110 P Sign Positive S
111 M Sign Negative

Timing

All call operation's take 17 (4,3,4,3,3) T-States, except for the conditional ones when the condition has not been met. In those instances it takes 10(4,3,3) T-States.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZPEPONP
CALL nn
CALL nn
CDnnnn317
CALL C,nn
DCnnnn317
CALL NC,nn
D4nnnn317
CALL Z,nn
CCnnnn317
CALL NZ,nn
C4nnnn317
CALL PE,nn
ECnnnn317
CALL PO,nn
E4nnnn317
CALL N,nn
FCnnnn317
CALL P,nn
F4nnnn317
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.3.4 - Return from Subroutine

76543210
 
\(PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2\)
RET
11001001
 
\(\begin{rcases} PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2 \end{rcases} \text{ if } ccc = true\)
RET ccc
11ccc000
Conditions
cccAbbrev Condition Flag
000NZ Non Zero Z
001Z Zero
010NC No Carry C
011C Carry
100 PO Parity Odd P/V
101 PE Parity Even
110 P Sign Positive S
111 M Sign Negative

Timing

The unconditional RET takes 10 (4,3,3) T-States. The conditional RET takes 17(5,3,3) T-States if the condition is true and 5 T-States if false and no return was performed.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZPEPONP
RET
RET
C9110
RET C
D8111
RET NC
D0111
RET Z
C8111
RET NZ
C0111
RET PE
E8111
RET PO
E0111
RET N
F8111
RET P
F0111
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.3.5 - RST

Invoke a Reset

RST performs a reset. Specifically it calls a routine at one of 8 addresses at the base of memory. It is the equivalent of performing a CALL to that address except the RST instruction is just 1 byte compared to 3 for CALL and is slightly faster.

\((SP-1) \longleftarrow PC_h \\(SP-2) \longleftarrow PC_l \\SP \longleftarrow SP-2 \\PC_h \longleftarrow 0\\PC_l \longleftarrow b*8\)

76543210
11b111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Issues with RST instructions

Assemblers use different conventions for the RST instruction. Some use numbers 0…7 whilst others use the address of the code invoked. They are all equivalent, as there are just 8 possible instruction codes.

Address OP Code RST Instruction Action
0000 C7 RST 0 Reset machine
0008 CF RST 1 RST 8 Operating System Specific
0010 D7 RST 2 RST $10 RST 16
0018 DF RST 3 RST $18 RST 24
0020 E7 RST 4 RST $20 RST 32
0028 EF RST 5 RST $28 RST 40
0030 F7 RST 6 RST $30 RST 48
0038 FF RST 7 RST $38 RST 56 Interrupt Handler in Mode 1
Flags Affected
None.
Opcode Matrix
Reset routine
01234567
RST
RST 0
C7111
RST 1
CF111
RST 2
D7111
RST 3
DF111
RST 4
E7111
RST 5
EF111
RST 6
F7111
RST 7
FF111
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.3.6 - Return from Interrupt

76543210
 
\(PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2\)
RETI
11101101ED
010011014D
 
\(PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2 \\ IFF_1 \longleftarrow IFF_2\)
RETN
11101101ED
0100010145
Flags Affected
None.
Opcode Matrix
RETIRETN
Op
RETI
ED4D214
RETN
ED45214
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Interrupt

3.4 - Stack

Push Pull onto the stack
76543210
 
\((SP-2) \longleftarrow qq_l, (SP-1) \longleftarrow qq_h\)
PUSH qq
11qq0101
 
\((SP-2) \longleftarrow IX_l, (SP-1) \longleftarrow IX_h\)
PUSH IX
11011101DD
11100101E5
 
\((SP-2) \longleftarrow IY_l, (SP-1) \longleftarrow IY_h\)
PUSH IY
11111101FD
11100101E5
 
\(qq_h \longleftarrow (SP-1), qq_l \longleftarrow (SP)\)
POP qq
11qq0001
 
\(IX_h \longleftarrow (SP-1), IX_l \longleftarrow (SP)\)
POP IX
11011101DD
11100001E1
 
\(IY_h \longleftarrow (SP-1), IY_l \longleftarrow (SP)\)
POP IY
11111101FD
11100001E1
Registers
Valueqq
00BC
01DE
10HL
11AF
Flags Affected
None.
Opcode Matrix
AFBCDEHLIXIY
PUSH
PUSH AF
F5111
PUSH BC
C5111
PUSH DE
D5111
PUSH HL
E5111
PUSH IX
DDE5215
PUSH IY
FDE5215
POP
POP AF
F1110
POP BC
C1110
POP DE
D1110
POP HL
E1110
POP IX
DDE1214
POP IY
FDE1214
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.5 - Rotate and Shift

Rotate Shift instructions

3.5.1 - RL Rotate bits left with Carry

Rotate bits left with carry
Visualisation of the RLA instruction
76543210
 
RLA
0001011117
 
RL r
11001011CB
00010r
 
RL (HL)
11001011CB
0001011016
 
RL (IX+d)
11011101DD
11001011CB
d
0001011016
 
RL (IY+d)
11111101FD
11001011CB
d
0001011016
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 7 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RL
RLA
1714









RL
RL A
CB1728
RL B
CB1028
RL C
CB1128
RL D
CB1228
RL E
CB1328
RL H
CB1428
RL L
CB1528
RL (HL)
CB16215
RL (IX+d)
DDCBnn16423
RL (IY+d)
FDCBnn16423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.5.2 - RLC Rotate bits left with Carry

Rotate bits left with carry
Visualisation of the RLC instruction
76543210
 
RLCA
0000011107
 
RLC r
11001011CB
00000r
 
RLC (HL)
11001011CB
0000011006
 
RLC (IX+d)
11011101DD
11001011CB
d
0000011006
 
RLC (IY+d)
11111101FD
11001011CB
d
0000011006
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 7 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RLC
RLCA
0714









RLC
RLC A
CB0728
RLC B
CB0028
RLC C
CB0128
RLC D
CB0228
RLC E
CB0328
RLC H
CB0428
RLC L
CB0528
RLC (HL)
CB0628
RLC (IX+d)
DDCBnn06423
RLC (IY+d)
FDCBnn06423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.5.3 - RR Rotate bits right with Carry

Rotate bits right with carry
Visualisation of the RRA instruction
76543210
 
RRA
000111111F
 
RR r
11001011CB
00011r
 
RR (HL)
11001011CB
000111101E
 
RR(IX+d)
11011101DD
11001011CB
d
000111101E
 
RR (IY+d)
11111101FD
11001011CB
d
000111101E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RR
RRA
1F14









RR
RR A
CB1F28
RR B
CB1828
RR C
CB1928
RR D
CB1A28
RR E
CB1B28
RR H
CB1C28
RR L
CB1D28
RR (HL)
CB1E215
RR (IX+d)
DDCBnn1E423
RR (IY+d)
FDCBnn1E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.5.4 - RRC Rotate bits right with Carry

Rotate bits left with carry
Visualisation of the RRC instruction
76543210
 
RRCA
000011110F
 
RRC r
11001011CB
00001r
 
RRC (HL)
11001011CB
000011100E
 
RRC (IX+d)
11011101DD
11001011CB
d
000011100E
 
RRC (IY+d)
11111101FD
11001011CB
d
000011100E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RRC
RRCA
0F14









RRC
RRC A
CB0F28
RRC B
CB0828
RRC C
CB0928
RRC D
CB0A28
RRC E
CB0B28
RRC H
CB0C28
RRC L
CB0D28
RRC (HL)
CB0E215
RRC (IX+d)
DDCBnn0E423
RRC (IY+d)
FDCBnn0E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.5.5 - SLA Shift bits left with Carry

Shift bits left with carry
Visualisation of the SLA instruction
76543210
 
SLA r
11001011CB
00100r
 
SLA (HL)
11001011CB
0010011026
 
SLA (IX+d)
11011101DD
11001011CB
d
0010011026
 
SLA (IY+d)
11111101FD
11001011CB
d
0010011026
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 7 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
SLA
SLA A
CB2728
SLA B
CB2028
SLA C
CB2128
SLA D
CB2228
SLA E
CB2328
SLA H
CB2428
SLA L
CB2528
SLA (HL)
CB26215
SLA (IX+d)
DDCBnn26423
SLA (IY+d)
FDCBnn26423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.5.6 - SRA Rotate bits right with Carry

Rotate bits right with carry, bit 7 remains unchanged
Visualisation of the SRA instruction

An arithmetic shift right 1 bit position is performed on the contents of operand. The contents of bit 0 are copied to the Carry flag and the previous contents of bit 7 remain unchanged.

76543210
 
SRA r
11001011CB
00101r
 
SRA (HL)
11001011CB
001011102E
 
SRA (IX+d)
11011101DD
11001011CB
d
001011102E
 
SRA (IY+d)
11111101FD
11001011CB
d
001011102E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
SRA
SRA A
CB2F28
SRA B
CB2828
SRA C
CB2928
SRA D
CB2A28
SRA E
CB2B28
SRA H
CB2C28
SRA L
CB2D28
SRA (HL)
CB2E215
SRA (IX+d)
DDCBnn2E423
SRA (IY+d)
FDCBnn2E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.5.7 - SRL Rotate bits right with Carry

Rotate bits right with carry, bit 7 is reset
Visualisation of the SRL instruction
76543210
 
SRL r
11001011CB
00111r
 
SRL (HL)
11001011CB
001111103E
 
SRL (IX+d)
11011101DD
11001011CB
d
001111103E
 
SRL (IY+d)
11111101FD
11001011CB
d
001111103E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
SRL
SRL A
CB3F28
SRL B
CB3828
SRL C
CB3928
SRL D
CB3A28
SRL E
CB3B28
SRL H
CB3C28
SRL L
CB3D28
SRL (HL)
CB3E215
SRL (IX+d)
DDCBnn3E423
SRL (IY+d)
FDCBnn3E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.5.8 - RLD

Rotate bit pairs in A and (HL) left
Visualisation of the RLD instruction
76543210
11101101ED
011011116F

The contents of the low-order four bits (bits 3, 2, 1, and 0) of the memory location (HL) are copied to the high-order four bits (7, 6, 5, and 4) of that same memory location; the previous contents of those high-order four bits are copied to the low-order four bits of the Accumulator (Register A); and the previous contents of the low-order four bits of the Accumulator are copied to the low-order four bits of memory location (HL). The contents of the high-order bits of the Accumulator are unaffected.

Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
Opcode Matrix
(HL)
Op
RLD (HL)
ED6F218
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.5.9 - RRD

Rotate bit pairs in A and (HL) right
Visualisation of the RRD instruction
76543210
11101101ED
0110011167

The contents of the low-order four bits (bits 3, 2, 1, and 0) of memory location (HL) are copied to the low-order four bits of the Accumulator (Register A). The previous contents of the low-order four bits of the Accumulator are copied to the high-order four bits (7, 6, 5, and 4) of location (HL); and the previous contents of the high-order four bits of (HL) are copied to the low-order four bits of (HL). The contents of the high-order bits of the Accumulator are unaffected.

Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
Opcode Matrix
(HL)
Op
RRD (HL)
ED67218
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.6 - Bit Manipulation

Bit Manipulation instructions

3.6.1 - BIT

Test if a specific bit is set
76543210
 
\(Z \longleftarrow \overline{r_b}\)
BIT b, r
11001011CB
01br
 
\(Z \longleftarrow \overline{(HL)_b}\)
BIT b, (HL)
11001011CB
01b110
 
\(Z \longleftarrow \overline{(IX+d)_b}\)
BIT b, (IX+d)
11011101DD
11001011CB
d
01b110
 
\(Z \longleftarrow \overline{(IY+d)_b}\)
BIT b, (IY+d)
11111101FD
11001011CB
d
01b110
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

Flags Affected
Flags
-z-h--n-
zset if the specified bit is 0
hset
nreset
Opcode Matrix
Source
ABCDEHL(HL)(IX+d)(IY+d)
BIT 0
BIT 0,A
CB4728
BIT 0,B
CB4028
BIT 0,C
CB4128
BIT 0,D
CB4228
BIT 0,E
CB4328
BIT 0,H
CB4428
BIT 0,L
CB4528
BIT 0,(HL)
CB46212
BIT 0,(IX+d)
DDCBnn46420
BIT 0,(IY+d)
FDCBnn46420
BIT 1
BIT 1,A
CB4F28
BIT 1,B
CB4828
BIT 1,C
CB4928
BIT 1,D
CB4A28
BIT 1,E
CB4B28
BIT 1,H
CB4C28
BIT 1,L
CB4D28
BIT 1,(HL)
CB4E212
BIT 1,(IX+d)
DDCBnn4E420
BIT 1,(IY+d)
FDCBnn4E420
BIT 2
BIT 2,A
CB5728
BIT 2,B
CB5028
BIT 2,C
CB5128
BIT 2,D
CB5228
BIT 2,E
CB5328
BIT 2,H
CB5428
BIT 2,L
CB5528
BIT 2,(HL)
CB56212
BIT 2,(IX+d)
DDCBnn56420
BIT 2,(IY+d)
FDCBnn56420
BIT 3
BIT 3,A
CB5F28
BIT 3,B
CB5828
BIT 3,C
CB5928
BIT 3,D
CB5A28
BIT 3,E
CB5B28
BIT 3,H
CB5C28
BIT 3,L
CB5D28
BIT 3,(HL)
CB5E212
BIT 3,(IX+d)
DDCBnn5E420
BIT 3,(IY+d)
FDCBnn5E420
BIT 4
BIT 4,A
CB6728
BIT 4,B
CB6028
BIT 4,C
CB6128
BIT 4,D
CB6228
BIT 4,E
CB6328
BIT 4,H
CB6428
BIT 4,L
CB6528
BIT 4,(HL)
CB66212
BIT 4,(IX+d)
DDCBnn66420
BIT 4,(IY+d)
FDCBnn66420
BIT 5
BIT 5,A
CB6F28
BIT 5,B
CB6828
BIT 5,C
CB6928
BIT 5,D
CB6A28
BIT 5,E
CB6B28
BIT 5,H
CB6C28
BIT 5,L
CB6D28
BIT 5,(HL)
CB6E212
BIT 5,(IX+d)
DDCBnn6E420
BIT 5,(IY+d)
FDCBnn6E420
BIT 6
BIT 6,A
CB7728
BIT 6,B
CB7028
BIT 6,C
CB7128
BIT 6,D
CB7228
BIT 6,E
CB7328
BIT 6,H
CB7428
BIT 6,L
CB7528
BIT 6,(HL)
CB76212
BIT 6,(IX+d)
DDCBnn76420
BIT 6,(IY+d)
FDCBnn76420
BIT 7
BIT 7,A
CB7F28
BIT 7,B
CB7828
BIT 7,C
CB7928
BIT 7,D
CB7A28
BIT 7,E
CB7B28
BIT 7,H
CB7C28
BIT 7,L
CB7D28
BIT 7,(HL)
CB7E212
BIT 7,(IX+d)
DDCBnn7E420
BIT 7,(IY+d)
FDCBnn7E420
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.6.2 - RES

Reset a specific bit
76543210
 
\(r_b \longleftarrow 0\)
RES b, r
11001011CB
10br
 
\((HL)_b \longleftarrow 0\)
RES b, (HL)
11001011CB
10b110
 
\((IX+d)_b \longleftarrow 0\)
RES b, (IX+d)
11011101DD
11001011CB
d
10b110
 
\((IY+d)_b \longleftarrow 0\)
RES b, (IY+d)
11111101FD
11001011CB
d
10b110
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

Flags Affected
None.
Opcode Matrix
Source
ABCDEHL(HL)(IX+d)(IY+d)
RES 0
RES 0,A
CB8728
RES 0,B
CB8028
RES 0,C
CB8128
RES 0,D
CB8228
RES 0,E
CB8328
RES 0,H
CB8428
RES 0,L
CB8528
RES 0,(HL)
CB86215
RES 0,(IX+d)
DDCBnn86423
RES 0,(IY+d)
FDCBnn86423
RES 1
RES 1,A
CB8F28
RES 1,B
CB8828
RES 1,C
CB8928
RES 1,D
CB8A28
RES 1,E
CB8B28
RES 1,H
CB8C28
RES 1,L
CB8D28
RES 1,(HL)
CB8E215
RES 1,(IX+d)
DDCBnn8E423
RES 1,(IY+d)
FDCBnn8E423
RES 2
RES 2,A
CB9728
RES 2,B
CB9028
RES 2,C
CB9128
RES 2,D
CB9228
RES 2,E
CB9328
RES 2,H
CB9428
RES 2,L
CB9528
RES 2,(HL)
CB96215
RES 2,(IX+d)
DDCBnn96423
RES 2,(IY+d)
FDCBnn96423
RES 3
RES 3,A
CB9F28
RES 3,B
CB9828
RES 3,C
CB9928
RES 3,D
CB9A28
RES 3,E
CB9B28
RES 3,H
CB9C28
RES 3,L
CB9D28
RES 3,(HL)
CB9E215
RES 3,(IX+d)
DDCBnn9E423
RES 3,(IY+d)
FDCBnn9E423
RES 4
RES 4,A
CBA728
RES 4,B
CBA028
RES 4,C
CBA128
RES 4,D
CBA228
RES 4,E
CBA328
RES 4,H
CBA428
RES 4,L
CBA528
RES 4,(HL)
CBA6215
RES 4,(IX+d)
DDCBnnA6423
RES 4,(IY+d)
FDCBnnA6423
RES 5
RES 5,A
CBAF28
RES 5,B
CBA828
RES 5,C
CBA928
RES 5,D
CBAA28
RES 5,E
CBAB28
RES 5,H
CBAC28
RES 5,L
CBAD28
RES 5,(HL)
CBAE215
RES 5,(IX+d)
DDCBnnAE423
RES 5,(IY+d)
FDCBnnAE423
RES 6
RES 6,A
CBB728
RES 6,B
CBB028
RES 6,C
CBB128
RES 6,D
CBB228
RES 6,E
CBB328
RES 6,H
CBB428
RES 6,L
CBB528
RES 6,(HL)
CBB6215
RES 6,(IX+d)
DDCBnnB6423
RES 6,(IY+d)
FDCBnnB6423
RES 7
RES 7,A
CBBF28
RES 7,B
CBB828
RES 7,C
CBB928
RES 7,D
CBBA28
RES 7,E
CBBB28
RES 7,H
CBBC28
RES 7,L
CBBD28
RES 7,(HL)
CBBE215
RES 7,(IX+d)
DDCBnnBE423
RES 7,(IY+d)
FDCBnnBE423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.6.3 - SET

Set a specific bit
76543210
 
\(r_b \longleftarrow 1\)
SET b, r
11001011CB
11br
 
\((HL)_b \longleftarrow 1\)
SET b, (HL)
11001011CB
11b110
 
\((IX+d)_b \longleftarrow 1\)
SET b, (IX+d)
11011101DD
11001011CB
d
11b110
 
\((IY+d)_b \longleftarrow 1\)
SET b, (IY+d)
11111101FD
11001011CB
d
11b110
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

Flags Affected
None.
Opcode Matrix
Source
ABCDEHL(HL)(IX+d)(IY+d)
SET 0
SET 0,A
CBC728
SET 0,B
CBC028
SET 0,C
CBC128
SET 0,D
CBC228
SET 0,E
CBC328
SET 0,H
CBC428
SET 0,L
CBC528
SET 0,(HL)
CBC6215
SET 0,(IX+d)
DDCBnnC6423
SET 0,(IY+d)
FDCBnnC6423
SET 1
SET 1,A
CBCF28
SET 1,B
CBC828
SET 1,C
CBC928
SET 1,D
CBCA28
SET 1,E
CBCB28
SET 1,H
CBCC28
SET 1,L
CBCD28
SET 1,(HL)
CBCE215
SET 1,(IX+d)
DDCBnnCE423
SET 1,(IY+d)
FDCBnnCE423
SET 2
SET 2,A
CBD728
SET 2,B
CBD028
SET 2,C
CBD128
SET 2,D
CBD228
SET 2,E
CBD328
SET 2,H
CBD428
SET 2,L
CBD528
SET 2,(HL)
CBD6215
SET 2,(IX+d)
DDCBnnD6423
SET 2,(IY+d)
FDCBnnD6423
SET 3
SET 3,A
CBDF28
SET 3,B
CBD828
SET 3,C
CBD928
SET 3,D
CBDA28
SET 3,E
CBDB28
SET 3,H
CBDC28
SET 3,L
CBDD28
SET 3,(HL)
CBDE215
SET 3,(IX+d)
DDCBnnDE423
SET 3,(IY+d)
FDCBnnDE423
SET 4
SET 4,A
CBE728
SET 4,B
CBE028
SET 4,C
CBE128
SET 4,D
CBE228
SET 4,E
CBE328
SET 4,H
CBE428
SET 4,L
CBE528
SET 4,(HL)
CBE6215
SET 4,(IX+d)
DDCBnnE6423
SET 4,(IY+d)
FDCBnnE6423
SET 5
SET 5,A
CBEF28
SET 5,B
CBE828
SET 5,C
CBE928
SET 5,D
CBEA28
SET 5,E
CBEB28
SET 5,H
CBEC28
SET 5,L
CBED28
SET 5,(HL)
CBEE215
SET 5,(IX+d)
DDCBnnEE423
SET 5,(IY+d)
FDCBnnEE423
SET 6
SET 6,A
CBF728
SET 6,B
CBF028
SET 6,C
CBF128
SET 6,D
CBF228
SET 6,E
CBF328
SET 6,H
CBF428
SET 6,L
CBF528
SET 6,(HL)
CBF6215
SET 6,(IX+d)
DDCBnnF6423
SET 6,(IY+d)
FDCBnnF6423
SET 7
SET 7,A
CBFF28
SET 7,B
CBF828
SET 7,C
CBF928
SET 7,D
CBFA28
SET 7,E
CBFB28
SET 7,H
CBFC28
SET 7,L
CBFD28
SET 7,(HL)
CBFE215
SET 7,(IX+d)
DDCBnnFE423
SET 7,(IY+d)
FDCBnnFE423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.7 - Exchanges

Exchange registers

These instructions exchange values between registers.

76543210
 
\(AF \longleftrightarrow AF'\)
EX AF, AF'
0000100008
 
\(BC \longleftrightarrow BC', DE \longleftrightarrow DE', HL \longleftrightarrow HL'\)
EXX
11011001D9
 
\(DE \longleftrightarrow HL\)
EX DE, HL
11101011EB
 
\(H \longleftrightarrow (SP+1), L \longleftrightarrow (SP)\)
EX (SP), HL
11100011E3
 
\(IX_h \longleftrightarrow (SP+1), IX_l \longleftrightarrow (SP)\)
EX (SP), IX
11011101DD
11100011E3
 
\(IY_h \longleftrightarrow (SP+1), IY_l \longleftrightarrow (SP)\)
EX (SP), IY
11111101FD
11100011E3

EX AF, AF' (0x08) allows the programmer to switch between the two pairs of Accumulator flag registers.

EX DE, HL (0xEB) exchanges the values between those two registers.

EXX (0xD9) allows the programmer to switch BC, DE and HL and BC', DE' and HL' register pairs.

Internally these instructions toggles a flip-flop which determines which register or register set is the active one. This minimises how long the instruction takes as no data is transferred - just a single bit changes state.

EX (SP),HL exchanges HL with the last value pushed on the stack.

Flags Affected
None.
Opcode Matrix
AF'HLIXIYBC',DE',HL'
AF
EX AF, AF'
0814




DE

EX DE, HL
EB14



(SP)

EX (SP), HL
E3119
EX (SP), IX
DDE3223
EX (SP), IY
FDE3223

BC,DE,HL




EXX
D914
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

3.8 - Block Copy or Search of memory

Copy or search block of memory

3.8.1 - Block Copy

Copy block of memory

The Block copy instructions allow for data to be moved around in memory. The programmer needs to configure the 16 bit registers to define the properties of the move: HL is the source address to copy from; DE is the destination address to copy to; BC is the number of bytes to copy.

\(\begin{rcases} \begin{rcases} HL \longleftarrow HL+1 \\ DE \longleftarrow DE+1 \end{rcases} \text{ if } D = 0\\ \begin{rcases} HL \longleftarrow HL-1 \\DE \longleftarrow DE-1 \end{rcases} \text{ if } D=1 \\BC \longleftarrow BC-1 \end{rcases} \text{repeat while } \begin{cases} L=1\\BC \not = 0 \end{cases}\)

76543210
11101101ED
101LD000

D 0=Increment, 1=Decrement HL after each iteration.

L If set then if \( BC \not = 0 \) at the end if the instruction then \( PC \longleftarrow PC - 2 \) so that the instruction is repeated.
If BC=0 at start of a repeatable instruction then 65536 iterations will occur.

The LD* instructions then perform the equivalent of the following:

  1. Copy a byte of memory from (HL) to (DE)
  2. Decrement BC by one
  3. HL and DE are either incremented (for LDI/LDIR) or decremented (for LDD/LDDR) by one.
  4. The LDIR and LDDR instructions will loop back to step one if \( BC \not = 0 \)

Timing

For the non-repeating instructions, they take 16(4,4,3,5) T-States to execute.

For the repeating instructions, they take either 21(4,4,3,5,5) T-States when they loop and 16(4,4,3,5) T-States when terminating.

Also note, that for these instructions the timing is for each iteration, not for the entire run. So if LDIR is run with BC=4 then the number of T-States for the entire operation would take 79(21+21+21+16) T-States.

Flags Affected
Flags
---h-p/v--
hReset
p/vNon-repeating: Set if BC-1 != 0, otherwise reset
Repeating: N/A as BC=0 after instruction completes
Opcode Matrix
IncrementDecrement
Single Copy
LDI
EDA0216
LDD
EDA8216
Repeat Copy
LDIR
EDB0221
LDDR
EDB8221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.8.2 - Block Search of memory

Search block of memory

The Block compare instructions allow for data to be searched for in memory. The programmer needs to configure the following registers to define the properties of the search: HL is the source address to search from; BC is the number of bytes to search. A is set to the value to search for.

\(\begin{rcases} A-(HL) \\ HL \longleftarrow HL+1 \text{ if } D = 0\\ HL \longleftarrow HL-1 \text{ if } D=1 \\BC \longleftarrow BC-1 \end{rcases} \text{repeat while } \begin{cases} L=1\\A \not = (HL)\\BC \not = 0 \end{cases}\)

76543210
11101101ED
101LD001

D 0=Increment, 1=Decrement HL after each iteration.

L If set then if \( BC \not = 0 \) at the end if the instruction then \( PC \longleftarrow PC - 2 \) so that the instruction is repeated.
If BC=0 at start of a repeatable instruction then 65536 iterations will occur.

The CP* instructions compare memory against the Accumulator

  1. Calculate difference between A and content of memory in (HL) to set/clear Z flag
  2. Decrement BC by one
  3. HL is either incremented (for CPI/CPIR) or decremented (for CPD/CPDR) by one.
  4. The CPIR and CPDR instructions will loop back to step one if \( A-(HL) \not = 0 \And BC \not = 0 \)
    If the value was found them HL will be set to the byte after or before it depending on the direction being used.

Timing

For the non-repeating instructions, they take 16(4,4,3,5) T-States to execute.

For the repeating instructions, they take either 21(4,4,3,5,5) T-States when they loop and 16(4,4,3,5) T-States when terminating.

Also note, that for these instructions the timing is for each iteration, not for the entire run. So if LDIR is run with BC=4 then the number of T-States for the entire operation would take 79(21+21+21+16) T-States.

Flags Affected
Flags
sz-h-p/v--
sSet if result is negative
zSet if A = (HL)
hBorrow from bit 4, otherwise reset
p/vNon-repeating: Set if BC-1 != 0, otherwise reset
Repeating: N/A as BC=0 after instruction completes
Opcode Matrix
IncrementDecrement
Single Search
CPI
EDA1216
CPD
EDA9216
Repeat Search
CPIR
EDB1221
CPDR
EDB9221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

3.9 - Input/Output

Input Output instructions

3.9.1 - IN A, (n)

Read from port and store in A

\(A \longleftarrow (n)\)

76543210
11011011DB
n

This instruction places n onto the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of the Accumulator also appear on the top half (A8…A15) of the address bus at this time. One byte from the selected port is placed on the data bus and written to the Accumulator (Register A).

Flags Affected
None.
Opcode Matrix
A
IN (n)
IN A,(n)
DBnn211
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.9.2 - IN r,(C)

Read from port in C and store in a specific register
76543210
 
\(r \longleftarrow (C)\)
IN r, (C)
11101101ED
01r000
 
\(F \longleftarrow (C)\)
IN F, (C)
11101101ED
0111000070
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

The contents of Register C are placed on the bottom half (A0…7) of the address bus to select the I/O device at one of 256 possible ports. The contents of Register B are placed on the top half (A8…A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to register r in the CPU.

There is an undocumented code where r=%110 which sets the flag register.

This is actually documented in Zilog's Z80 CPU User Manual, 2016 edition Page 296. For this reason it's included on this page and not in the Undocumented instruction section.

Flags Affected
Flags
sz-h-p/vn-
sset if input data is negative
zset if input data is 0
hreset
p/vset if parity is even, reset if odd
nreset
Opcode Matrix
ABCDEHLF
IN (C)
IN A,(C)
ED7B212
IN B,(C)
ED40212
IN C,(C)
ED48212
IN D,(C)
ED50212
IN E,(C)
ED58212
IN H,(C)
ED60212
IN L,(C)
ED68212
IN F,(C)
ED70212
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special Undocumented

3.9.3 - OUT (C), r

Write r to a port
76543210
 
\((C) \longleftarrow r\)
OUT (C), r
11101101ED
01r001
 
\((C) \longleftarrow F\)
OUT (C), F
11101101ED
0111000171
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

The contents of Register C are placed on the bottom half (A0…7) of the address bus to select the I/O device at one of 256 possible ports.

The contents of Register B are placed on the top half (A8…A15) of the address bus at this time.

Then the byte contained in r is placed on the data bus and written to the selected peripheral device.

There is an undocumented code where r=%110 which writes the flag register.

Unlike it's IN F, (C) counterpart, this instruction is completely undocumented, but it's here not in the undocumented section to be consistent.

Flags Affected
None.
Opcode Matrix
ABCDEHLF
OUT (C)
OUT (C),A
ED79212
OUT (C),B
ED41212
OUT (C),C
ED49212
OUT (C),D
ED51212
OUT (C),E
ED59212
OUT (C),H
ED61212
OUT (C),L
ED69212
OUT (C),F
ED71212
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special Undocumented

3.9.4 - OUT (n), A

Write A to a port

\((n) \longleftarrow A\)

76543210
11010011D3
n

This instruction places n onto the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.

The contents of the Accumulator also appear on the top half (A8…A15) of the address bus at this time.

Then the byte contained in the Accumulator is placed on the data bus and written to the selected peripheral device.

Flags Affected
None.
Opcode Matrix
A
OUT (n)
OUT (n),A
D3nn211
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.9.5 - Block read from port

\(\begin{rcases} (HL) \longleftarrow (C)\\HL \longleftarrow HL+1 \text{ if } D = 0\\HL \longleftarrow HL-1 \text{ if } D = 1\\B \longleftarrow B-1 \end{rcases} \text{repeat while } L=1 \And B \not = 0\)

76543210
11101101ED
101LD010

D 0=Increment, 1=Decrement HL after each iteration

L If set then if \(B \not = 0\) then \(PC \longleftarrow PC-2\) so that the instruction is repeated.

The contents of Register C are placed on the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.

Register B can be used as a byte counter, and its contents are placed on the top half (A8…15) of the address bus at this time.

Then one byte from the selected port is placed on the data bus and written to the CPU.

The contents of the HL register pair are then placed on the address bus and the input byte is written to the corresponding location of memory.

Finally, the byte counter is decremented and register pair HL is incremented.

Flags Affected
Flags
-z----n-
zset if B = 0, always true for repeat operations
nset
Opcode Matrix
IncrementDecrement
Single
INI
EDA2216
IND
EDAA216
Repeat
INIR
EDB2221
INDR
EDBA221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.9.6 - Block write to port

\(\begin{rcases} (C) \longleftarrow (HL)\\HL \longleftarrow HL+1 \text{ if } D = 0\\HL \longleftarrow HL-1 \text{ if } D = 1\\B \longleftarrow B-1 \end{rcases} \text{repeat while } L=1 \And B \not = 0\)

76543210
11101101ED
101LD011

D 0=Increment, 1=Decrement HL after each iteration

L If set then if \(B \not = 0\) then \(PC \longleftarrow PC-2\) so that the instruction is repeated.

The contents of Register C are placed on the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.

Register B can be used as a byte counter, and its contents are placed on the top half (A8…15) of the address bus at this time.

Then one byte from the address pointed to by HL is placed on the data bus and written to the port.

Finally, the byte counter is decremented and register pair HL is incremented.

Flags Affected
Flags
-z----n-
zset if B = 0, always true for repeat operations
nset
Opcode Matrix
IncrementDecrement
Single
OUTI
EDA3216
OUTD
EDAB216
Repeat
OUTIR
EDB3221
OUTDR
EDBB221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.10 - Miscellaneous Instructions

Miscellaneous instructions

3.10.1 - NOP No Operation

76543210
0000000000
Opcode Matrix
NOP
OP
NOP
0014
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.10.2 - CPL Invert Accumulator

\(A \longleftarrow \overline{A}\)

76543210
001011112F
Flags Affected
Flags
---h--n-
hset
nset
Opcode Matrix
CPL
OP
CPL
2F14
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.10.3 - NEG Negate Accumulator (two's compliment)

\(A \longleftarrow 0 - A\)

76543210
11101101ED
0100010044
Flags Affected
Flags
sz-h-p/vnc
sset if result is negative
zset if result is 0
hset if borrow from bit 4
p/vset if Accumulator was 0x80 before operation
nset
cset if Accumulator was not 0x00 before operation
Opcode Matrix
NEG
OP
NEG
ED4424
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.10.4 - HALT the cpu

76543210
0111011076
Opcode Matrix
HALT
OP
HALT
7614
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.10.5 - CCF Compliment Carry Flag

Invert Carry Flag

\(CY \longleftarrow \overline{CY}\)

76543210
001111113F
Flags Affected
Flags
---h---c
hprevious carry is copied
cset if C was 0, reset if C was 1
Opcode Matrix
CCF
OP
CCF
3F14
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.10.6 - SCF Set Carry Flag

Set Carry Flag

\(CY \longleftarrow 1\)

76543210
0011011137
Flags Affected
Flags
---h--nc
hreset
nreset
cset
Opcode Matrix
CPLNEGCCFSCF
OP
CPL
2F14
NEG
ED4424
CCF
3F14
SCF
3714
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.10.7 - DI EI Interrupt enable

Enable/Disable interrupts
76543210
 
\(IFF \longleftarrow 0\)
DI
11110011
 
\(IFF \longleftarrow 1\)
EI
11111011
Opcode Matrix
EIDI
OP
EI
FB14
DI
F314
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Interrupt

3.10.8 - IM Interrupt Mode

Select interrupt mode
76543210
11101101ED
010QQ110

Note: Only modes 0, 1 and 2 are valid for IM n.

Opcode Matrix
IM0IM1IM2
OP
IM0
ED4628
IM1
ED5628
IM2
ED5E28
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Interrupt

3.10.9 - DAA

Adjust accumulator for BCD addition and subtraction operations

\(@\)

76543210
0010011127
Flags Affected
Flags
-z-h-p/v-c
zSet if Accumulator is 0
hVaries
p/vSet if Accumulator parity is even, reset if odd
cVaries
Opcode Matrix
DAA
OP
DAA
2714
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

3.11 - Undocumented Instructions

Undocumented instructions - use with care

Like most early microprocessors, the Z80 has it's own set of undocumented instructions.

Most of these either do something that's not useful, or they do something that would at first seem to be odd in why they were implemented in the first place.

In most instances, they exist due to how the processor is implemented in silicon. Where an instruction is decoded, there are free bits so if something tried to use that code then the processor would just do as it's told as it wouldn't know otherwise.

Be aware, these usually work on a physical chip due to it requiring the actual instruction decoding to provide these instructions.

They will most likely not work in an emulator as they would perform the decoding in software using lookup tables, so wouldn't implement anything that's not documented.

These may or may not work on actual chips. For example, on the 6502 there were plenty of undocumented instructions that were replaced in the 65C02 with NOP instructions.

These are provided here for reference only.

Overview

Most of the undocumented instructions fall under some simple rules:

CB

Only codes 0xCB30…0xCB37 are undocumented but implement a Shift Logical Left instruction where bit 0 is set post shift.

DDCB & FDCB

For opcodes with the 0xDDCB and 0xFDCB prefixes the instructions store the result in one of the 8-bit registers based on the lower 3 bits of the opcode: B=000, C=001, D=010, E=011, H=100, L=101 and A=111.

The officially documented codes all have 110 as the lower 3 bits and do not store the result in any register.

All of these instructions with the 0xDDCB prefix operate against the IX register (IY for 0xFDBC).

The only exception to this rule is opcodes 0x40…0x7F which are the bit text operations. As these only test the memory location they do not create a result so all the undocumented versions are identical to the official instructions.

DD & FD

Officially the 0xDD and 0xFD prefixes cause any instruction that references (HL) to instead work against the IX & IY registers with a displacement, 0xDD for IX and 0xFD for IY.

The undocumented instructions allows for instructions that refer to just H or L can also be used to access the upper or lower 8-bit components of IX and IY themselves.

ED

There are a few undocumented instructions with this prefix, but they simply emulate existing instructions.

The exception to this are the IN F, (C) and OUT (C), F instructions which are described below.

When is undocumented actually documented?

One oddity is the undocumented IN F,(C)0xED70 instruction which performs an IN from an I/O port but stores the result into the Flags register. This instruction is actually documented in Zilogs own documentation (2016 PDF). For this reason, that instruction is listed on the IN r, (C) page and not in this section.

It's OUT (C), F0xED71 equivalent is listed under OUT (C), r for consistency, even though that instruction is completely undocumented.

3.11.1 - Dual Shift Operations

Undocumented instructions that perform two actions at the same time

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official RLC (IX+nn)0xDDCBnn06 instruction operates on a specific memory address, however the undocumented RLC B,(IX+nn)0xDDCBnn00 instruction does the same thing but then copies the result into the B register.

3.11.1.1 - RL Rotate bits left with Carry and store in register

Undocumented Rotate bits left with carry and store in register

This instruction performs an RL (IX+dd) or RL (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RL instruction

76543210
 
RL r,(IX+d)
11011101DD
11001011CB
d
00010r
 
RL r,(IY+d)
11111101FD
11001011CB
d
00010r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RL A,(IX+d)
DDCBnn17
RL B,(IX+d)
DDCBnn10
RL C,(IX+d)
DDCBnn11
RL D,(IX+d)
DDCBnn12
RL E,(IX+d)
DDCBnn13
RL H,(IX+d)
DDCBnn14
RL L,(IX+d)
DDCBnn15
(IY+d)
RL A,(IY+d)
FDCBnn17
RL B,(IY+d)
FDCBnn10
RL C,(IY+d)
FDCBnn11
RL D,(IY+d)
FDCBnn12
RL E,(IY+d)
FDCBnn13
RL H,(IY+d)
FDCBnn14
RL L,(IY+d)
FDCBnn15
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.1.2 - RLC Rotate bits left with Carry and store in register

Undocumented Rotate bits left with carry and store in register

This instruction performs an RLC (IX+dd) or RLC (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RLC instruction

76543210
 
RLC r,(IX+d)
11011101DD
11001011CB
d
00000r
 
RLC r,(IY+d)
11111101FD
11001011CB
d
00000r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RLC A,(IX+d)
DDCBnn07
RLC B,(IX+d)
DDCBnn00
RLC C,(IX+d)
DDCBnn01
RLC D,(IX+d)
DDCBnn02
RLC E,(IX+d)
DDCBnn03
RLC H,(IX+d)
DDCBnn04
RLC L,(IX+d)
DDCBnn05
(IY+d)
RLC A,(IY+d)
FDCBnn07
RLC B,(IY+d)
FDCBnn00
RLC C,(IY+d)
FDCBnn01
RLC D,(IY+d)
FDCBnn02
RLC E,(IY+d)
FDCBnn03
RLC H,(IY+d)
FDCBnn04
RLC L,(IY+d)
FDCBnn05
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.1.3 - RR Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an RR (IX+dd) or RR (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RR instruction

76543210
 
RR r,(IX+d)
11011101DD
11001011CB
d
00011r
 
RR r,(IY+d)
11111101FD
11001011CB
d
00011r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RR A,(IX+d)
DDCBnn1F
RR B,(IX+d)
DDCBnn18
RR C,(IX+d)
DDCBnn19
RR D,(IX+d)
DDCBnn1A
RR E,(IX+d)
DDCBnn1B
RR H,(IX+d)
DDCBnn1C
RR L,(IX+d)
DDCBnn1D
(IY+d)
RR A,(IY+d)
FDCBnn1F
RR B,(IY+d)
FDCBnn18
RR C,(IY+d)
FDCBnn19
RR D,(IY+d)
FDCBnn1A
RR E,(IY+d)
FDCBnn1B
RR H,(IY+d)
FDCBnn1C
RR L,(IY+d)
FDCBnn1D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.1.4 - RRC Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an RRC (IX+dd) or RRC (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RRC instruction

76543210
 
RRC r,(IX+d)
11011101DD
11001011CB
d
00001r
 
RRC r,(IY+d)
11111101FD
11001011CB
d
00001r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RRC A,(IX+d)
DDCBnn0F
RRC B,(IX+d)
DDCBnn08
RRC C,(IX+d)
DDCBnn09
RRC D,(IX+d)
DDCBnn0A
RRC E,(IX+d)
DDCBnn0B
RRC H,(IX+d)
DDCBnn0C
RRC L,(IX+d)
DDCBnn0D
(IY+d)
RRC A,(IY+d)
FDCBnn0F
RRC B,(IY+d)
FDCBnn08
RRC C,(IY+d)
FDCBnn09
RRC D,(IY+d)
FDCBnn0A
RRC E,(IY+d)
FDCBnn0B
RRC H,(IY+d)
FDCBnn0C
RRC L,(IY+d)
FDCBnn0D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.1.5 - SLA Shift bits left with Carry and store in register

Undocumented Shift bits left with carry and store in register

This instruction performs an SLA (IX+dd) or SLA (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the SLA instruction

76543210
 
SLA r,(IX+d)
11011101DD
11001011CB
d
00100r
 
SLA r,(IY+d)
11111101FD
11001011CB
d
00100r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SLA A,(IX+d)
DDCBnn27
SLA B,(IX+d)
DDCBnn20
SLA C,(IX+d)
DDCBnn21
SLA D,(IX+d)
DDCBnn22
SLA E,(IX+d)
DDCBnn23
SLA H,(IX+d)
DDCBnn24
SLA L,(IX+d)
DDCBnn25
(IY+d)
SLA A,(IY+d)
FDCBnn27
SLA B,(IY+d)
FDCBnn20
SLA C,(IY+d)
FDCBnn21
SLA D,(IY+d)
FDCBnn22
SLA E,(IY+d)
FDCBnn23
SLA H,(IY+d)
FDCBnn24
SLA L,(IY+d)
FDCBnn25
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.1.6 - SLL Shift left Logical and store in register

Undocumented Shift left logical and store in register

This instruction performs an SLL (IX+dd) or SLL (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Note: This is an undocumented extension to an undocumented instruction.

Visualisation of the SLL instruction

76543210
 
SLL r,(IX+d)
11011101DD
11001011CB
d
00110r
 
SLL r,(IY+d)
11111101FD
11001011CB
d
00110r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SLL A,(IX+d)
DDCBnn37
SLL B,(IX+d)
DDCBnn30
SLL C,(IX+d)
DDCBnn31
SLL D,(IX+d)
DDCBnn32
SLL E,(IX+d)
DDCBnn33
SLL H,(IX+d)
DDCBnn34
SLL L,(IX+d)
DDCBnn35
(IY+d)
SLL A,(IY+d)
FDCBnn37
SLL B,(IY+d)
FDCBnn30
SLL C,(IY+d)
FDCBnn31
SLL D,(IY+d)
FDCBnn32
SLL E,(IY+d)
FDCBnn33
SLL H,(IY+d)
FDCBnn34
SLL L,(IY+d)
FDCBnn35
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.1.7 - SRA Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an SRA (IX+dd) or SRA (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the SRA instruction

76543210
 
SRA r,(IX+d)
11011101DD
11001011CB
d
00101r
 
SRA r,(IY+d)
11111101FD
11001011CB
d
00101r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SRA A,(IX+d)
DDCBnn2F
SRA B,(IX+d)
DDCBnn28
SRA C,(IX+d)
DDCBnn29
SRA D,(IX+d)
DDCBnn2A
SRA E,(IX+d)
DDCBnn2B
SRA H,(IX+d)
DDCBnn2C
SRA L,(IX+d)
DDCBnn2D
(IY+d)
SRA A,(IY+d)
FDCBnn2F
SRA B,(IY+d)
FDCBnn28
SRA C,(IY+d)
FDCBnn29
SRA D,(IY+d)
FDCBnn2A
SRA E,(IY+d)
FDCBnn2B
SRA H,(IY+d)
FDCBnn2C
SRA L,(IY+d)
FDCBnn2D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.1.8 - SRL Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an SRL (IX+dd) or SRL (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the SRL instruction

76543210
 
SRL r,(IX+d)
11011101DD
11001011CB
d
00111r
 
SRL r,(IY+d)
11111101FD
11001011CB
d
00111r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SRL A,(IX+d)
DDCBnn3F
SRL B,(IX+d)
DDCBnn38
SRL C,(IX+d)
DDCBnn39
SRL D,(IX+d)
DDCBnn3A
SRL E,(IX+d)
DDCBnn3B
SRL H,(IX+d)
DDCBnn3C
SRL L,(IX+d)
DDCBnn3D
(IY+d)
SRL A,(IY+d)
FDCBnn3F
SRL B,(IY+d)
FDCBnn38
SRL C,(IY+d)
FDCBnn39
SRL D,(IY+d)
FDCBnn3A
SRL E,(IY+d)
FDCBnn3B
SRL H,(IY+d)
FDCBnn3C
SRL L,(IY+d)
FDCBnn3D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.2 - IX and IY registers

Undocumented instructions for IX and IY registers

If an opcode works with the Registers HL, H or L then if that opcode is prefixed by 0xDD then it will also work on the appropriate IX, IXh or IXl registers, with some exceptions.

The 0xFD prefix would also work but for the IY, IYh or IYl registers

The exceptions are instructions like LD H,IXh or LD L,IYh where it isn't clear from the opcode which register the 0xFD or 0xDD prefix should operate against.

3.11.2.1 - LD IX undocumented instructions

Undocumented instructions for LD IX
Opcode Matrix
ABCDEnIXhIXl
A






LD A,IXh
DD7C
LD A,IXl
DD7D
B






LD B,IXh
DD44
LD B,IXl
DD45
C






LD C,IXh
DD4C
LD C,IXl
DD4D
D






LD D,IXh
DD54
LD D,IXl
DD55
E






LD E,IXh
DD5C
LD E,IXl
DD5D
IXh
LD IXh,A
DD67
LD IXh,B
DD60
LD IXh,C
DD61
LD IXh,D
DD62
LD IXh,E
DD63
LD IXh,n
DD26nn
LD IXh,IHh
DD64
LD IXh,IHl
DD65
IXl
LD IXl,A
DD6F
LD IXl,B
DD68
LD IXl,C
DD69
LD IXl,D
DD6A
LD IXl,E
DD6B
LD IXl,n
DD2Enn
LD IXl,IHh
DD6C
LD IXl,IHl
DD6D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.2.2 - LD IY undocumented instructions

Undocumented instructions for LD IY
Opcode Matrix
ABCDEnIYhIYl
A






LD A,IYh
FD7C
LD A,IYl
FD7D
B






LD B,IYh
FD44
LD B,IYl
FD45
C






LD C,IYh
FD4C
LD C,IYl
FD4D
D






LD D,IYh
FD54
LD D,IYl
FD55
E






LD E,IYh
FD5C
LD E,IYl
FD5D
IYh
LD IYh,A
FD67
LD IYh,B
FD60
LD IYh,C
FD61
LD IYh,D
FD62
LD IYh,E
FD63
LD IYh,n
FD26nn
LD IYh,IHh
FD64
LD IYh,IHl
FD65
IYl
LD IYl,A
FD6F
LD IYl,B
FD68
LD IYl,C
FD69
LD IYl,D
FD6A
LD IYl,E
FD6B
LD IYl,n
FD2Enn
LD IYl,IHh
FD6C
LD IYl,IHl
FD6D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.2.3 - Undocumented Math instructions with the IX register

Undocumented math instructions for IX register
Opcode Matrix
INCDECADD AADC ASUBSBC AANDXORORCP
IXh
INC IXh
DD24
DEC IXh
DD25
ADD A,IXh
DD84
ADC A,IXh
DD8C
SUB IXh
DD94
SBC A,IXh
DD9C
AND IXh
DDA4
XOR IXh
DDAC
OR IXh
DDB4
CP IXh
DDBC
IXl
INC IXl
DD2C
DEC IXl
DD2D
ADD A,IXl
DD85
ADC A,IXl
DD8D
SUB IXl
DD95
SBC A,IXl
DD9D
AND IXl
DDA5
XOR IXl
DDAD
OR IXl
DDB5
CP IXl
DDBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.2.4 - Undocumented Math instructions with the IY register

Undocumented math instructions for IY register
Opcode Matrix
INCDECADD AADC ASUBSBC AANDXORORCP
IYh
INC IYh
FD24
DEC IYh
FD25
ADD A,IYh
FD84
ADC A,IYh
FD8C
SUB IYh
FD94
SBC A,IYh
FD9C
AND IYh
FDA4
XOR IYh
FDAC
OR IYh
FDB4
CP IYh
FDBC
IYl
INC IYl
FD2C
DEC IYl
FD2D
ADD A,IYl
FD85
ADC A,IYl
FD8D
SUB IYl
FD95
SBC A,IYl
FD9D
AND IYl
FDA5
XOR IYl
FDAD
OR IYl
FDB5
CP IYl
FDBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.3 - SLL Shift Left Logical

Undocumented instruction to perform a logical left shift

The block CB30…CB37 is missing from the official list.

These instructions, usually denoted by the mnemonic SLL, Shift Left Logical, shift left the operand and make bit 0 always one.

These instructions are quite commonly used. For example, Bounder and Enduro Racer use them.

Some documents list this as SL1 instead of SLL due to it setting bit 0.

Visualisation of the SLL instruction
76543210
 
SLL r
11001011CB
00000r
 
SLL (HL)
11001011CB
0000011006
 
SLL (IX+d)
11011101DD
11001011CB
d
0000011006
 
SLL (IY+d)
11111101FD
11001011CB
d
0000011006
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Opcode Matrix
ABCDEHL(HL)(IX+dd)(IY+dd)
SLL
SLL A
CB37
SLL B
CB30
SLL C
CB31
SLL D
CB32
SLL E
CB33
SLL H
CB34
SLL L
CB35
SLL (HL)
CB36
SLL (IX+dd)
DDCBnn36
SLL (IY+dd)
FDCBnn36
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.4 - Test bit in (IX+d)

Undocumented BIT n,(IX+d)

Similar to the RES and SET instructions, there are undocumented instructions for BIT. Unlike the other, as BIT only tests a bit and does not change anything, these opcodes have the same behaviour to the officially documented BIT instruction.

76543210
 
\(Z \longleftarrow \overline{(IX+d)_b}\)
BIT b, (IX+d)
11011101DD
11001011CB
d
01br
 
\(Z \longleftarrow \overline{(IY+d)_b}\)
BIT b, (IY+d)
11111101FD
11001011CB
d
01br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

r=%110 does exist, it is the official, documented operation.

3.11.5 - RES Reset bit in (IX+d) and copy into register r

Undocumented Reset bit in (IX+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official RES 0,(IX+nn) instruction resets bit 0 on a specific memory address, however the undocumented RES B,0,(IX+nn)0xDDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IX+d)_b \longleftarrow 0 \\ r \longleftarrow (IX+d)\)

76543210
11011101DD
11001011CB
d
10br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
RES A,0,(IX+nn)
DDCBnn87
RES A,1,(IX+nn)
DDCBnn8F
RES A,2,(IX+nn)
DDCBnn97
RES A,3,(IX+nn)
DDCBnn9F
RES A,4,(IX+nn)
DDCBnnA7
RES A,5,(IX+nn)
DDCBnnAF
RES A,6,(IX+nn)
DDCBnnB7
RES A,7,(IX+nn)
DDCBnnBF
B
RES B,0,(IX+nn)
DDCBnn80
RES B,1,(IX+nn)
DDCBnn88
RES B,2,(IX+nn)
DDCBnn90
RES B,3,(IX+nn)
DDCBnn98
RES B,4,(IX+nn)
DDCBnnA0
RES B,5,(IX+nn)
DDCBnnA8
RES B,6,(IX+nn)
DDCBnnB0
RES B,7,(IX+nn)
DDCBnnB8
C
RES C,0,(IX+nn)
DDCBnn81
RES C,1,(IX+nn)
DDCBnn89
RES C,2,(IX+nn)
DDCBnn91
RES C,3,(IX+nn)
DDCBnn99
RES C,4,(IX+nn)
DDCBnnA1
RES C,5,(IX+nn)
DDCBnnA9
RES C,6,(IX+nn)
DDCBnnB1
RES C,7,(IX+nn)
DDCBnnB9
D
RES D,0,(IX+nn)
DDCBnn82
RES D,1,(IX+nn)
DDCBnn8A
RES D,2,(IX+nn)
DDCBnn92
RES D,3,(IX+nn)
DDCBnn9A
RES D,4,(IX+nn)
DDCBnnA2
RES D,5,(IX+nn)
DDCBnnAA
RES D,6,(IX+nn)
DDCBnnB2
RES D,7,(IX+nn)
DDCBnnBA
E
RES E,0,(IX+nn)
DDCBnn83
RES E,1,(IX+nn)
DDCBnn8B
RES E,2,(IX+nn)
DDCBnn93
RES E,3,(IX+nn)
DDCBnn9B
RES E,4,(IX+nn)
DDCBnnA3
RES E,5,(IX+nn)
DDCBnnAB
RES E,6,(IX+nn)
DDCBnnB3
RES E,7,(IX+nn)
DDCBnnBB
H
RES H,0,(IX+nn)
DDCBnn84
RES H,1,(IX+nn)
DDCBnn8C
RES H,2,(IX+nn)
DDCBnn94
RES H,3,(IX+nn)
DDCBnn9C
RES H,4,(IX+nn)
DDCBnnA4
RES H,5,(IX+nn)
DDCBnnAC
RES H,6,(IX+nn)
DDCBnnB4
RES H,7,(IX+nn)
DDCBnnBC
L
RES L,0,(IX+nn)
DDCBnn85
RES L,1,(IX+nn)
DDCBnn8D
RES L,2,(IX+nn)
DDCBnn95
RES L,3,(IX+nn)
DDCBnn9D
RES L,4,(IX+nn)
DDCBnnA5
RES L,5,(IX+nn)
DDCBnnAD
RES L,6,(IX+nn)
DDCBnnB5
RES L,7,(IX+nn)
DDCBnnBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.6 - RES Reset bit in (IY+d) and copy into register r

Undocumented Reset bit in (IY+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official RES 0,(IY+nn) instruction resets bit 0 on a specific memory address, however the undocumented RES B,0,(IY+nn)0xFDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IY+d)_b \longleftarrow 0 \\ r \longleftarrow (IY+d)\)

76543210
11111101FD
11001011CB
d
10br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
RES A,0,(IY+nn)
FDCBnn87
RES A,1,(IY+nn)
FDCBnn8F
RES A,2,(IY+nn)
FDCBnn97
RES A,3,(IY+nn)
FDCBnn9F
RES A,4,(IY+nn)
FDCBnnA7
RES A,5,(IY+nn)
FDCBnnAF
RES A,6,(IY+nn)
FDCBnnB7
RES A,7,(IY+nn)
FDCBnnBF
B
RES B,0,(IY+nn)
FDCBnn80
RES B,1,(IY+nn)
FDCBnn88
RES B,2,(IY+nn)
FDCBnn90
RES B,3,(IY+nn)
FDCBnn98
RES B,4,(IY+nn)
FDCBnnA0
RES B,5,(IY+nn)
FDCBnnA8
RES B,6,(IY+nn)
FDCBnnB0
RES B,7,(IY+nn)
FDCBnnB8
C
RES C,0,(IY+nn)
FDCBnn81
RES C,1,(IY+nn)
FDCBnn89
RES C,2,(IY+nn)
FDCBnn91
RES C,3,(IY+nn)
FDCBnn99
RES C,4,(IY+nn)
FDCBnnA1
RES C,5,(IY+nn)
FDCBnnA9
RES C,6,(IY+nn)
FDCBnnB1
RES C,7,(IY+nn)
FDCBnnB9
D
RES D,0,(IY+nn)
FDCBnn82
RES D,1,(IY+nn)
FDCBnn8A
RES D,2,(IY+nn)
FDCBnn92
RES D,3,(IY+nn)
FDCBnn9A
RES D,4,(IY+nn)
FDCBnnA2
RES D,5,(IY+nn)
FDCBnnAA
RES D,6,(IY+nn)
FDCBnnB2
RES D,7,(IY+nn)
FDCBnnBA
E
RES E,0,(IY+nn)
FDCBnn83
RES E,1,(IY+nn)
FDCBnn8B
RES E,2,(IY+nn)
FDCBnn93
RES E,3,(IY+nn)
FDCBnn9B
RES E,4,(IY+nn)
FDCBnnA3
RES E,5,(IY+nn)
FDCBnnAB
RES E,6,(IY+nn)
FDCBnnB3
RES E,7,(IY+nn)
FDCBnnBB
H
RES H,0,(IY+nn)
FDCBnn84
RES H,1,(IY+nn)
FDCBnn8C
RES H,2,(IY+nn)
FDCBnn94
RES H,3,(IY+nn)
FDCBnn9C
RES H,4,(IY+nn)
FDCBnnA4
RES H,5,(IY+nn)
FDCBnnAC
RES H,6,(IY+nn)
FDCBnnB4
RES H,7,(IY+nn)
FDCBnnBC
L
RES L,0,(IY+nn)
FDCBnn85
RES L,1,(IY+nn)
FDCBnn8D
RES L,2,(IY+nn)
FDCBnn95
RES L,3,(IY+nn)
FDCBnn9D
RES L,4,(IY+nn)
FDCBnnA5
RES L,5,(IY+nn)
FDCBnnAD
RES L,6,(IY+nn)
FDCBnnB5
RES L,7,(IY+nn)
FDCBnnBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.7 - SET bit in (IX+d) and copy into register r

Undocumented SET bit in (IX+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official SET 0,(IX+nn) instruction sets bit 0 on a specific memory address, however the undocumented SET B,0,(IX+nn)0xDDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IX+d)_b \longleftarrow 0 \\ r \longleftarrow (IX+d)\)

76543210
11111101DD
11001011CB
d
11br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
SET A,0,(IX+nn)
DDCBnnC7
SET A,1,(IX+nn)
DDCBnnCF
SET A,2,(IX+nn)
DDCBnnD7
SET A,3,(IX+nn)
DDCBnnDF
SET A,4,(IX+nn)
DDCBnnE7
SET A,5,(IX+nn)
DDCBnnEF
SET A,6,(IX+nn)
DDCBnnF7
SET A,7,(IX+nn)
DDCBnnFF
B
SET B,0,(IX+nn)
DDCBnnC0
SET B,1,(IX+nn)
DDCBnnC8
SET B,2,(IX+nn)
DDCBnnD0
SET B,3,(IX+nn)
DDCBnnD8
SET B,4,(IX+nn)
DDCBnnE0
SET B,5,(IX+nn)
DDCBnnE8
SET B,6,(IX+nn)
DDCBnnF0
SET B,7,(IX+nn)
DDCBnnF8
C
SET C,0,(IX+nn)
DDCBnnC1
SET C,1,(IX+nn)
DDCBnnC9
SET C,2,(IX+nn)
DDCBnnD1
SET C,3,(IX+nn)
DDCBnnD9
SET C,4,(IX+nn)
DDCBnnE1
SET C,5,(IX+nn)
DDCBnnE9
SET C,6,(IX+nn)
DDCBnnF1
SET C,7,(IX+nn)
DDCBnnF9
D
SET D,0,(IX+nn)
DDCBnnC2
SET D,1,(IX+nn)
DDCBnnCA
SET D,2,(IX+nn)
DDCBnnD2
SET D,3,(IX+nn)
DDCBnnDA
SET D,4,(IX+nn)
DDCBnnE2
SET D,5,(IX+nn)
DDCBnnEA
SET D,6,(IX+nn)
DDCBnnF2
SET D,7,(IX+nn)
DDCBnnFA
E
SET E,0,(IX+nn)
DDCBnnC3
SET E,1,(IX+nn)
DDCBnnCB
SET E,2,(IX+nn)
DDCBnnD3
SET E,3,(IX+nn)
DDCBnnDB
SET E,4,(IX+nn)
DDCBnnE3
SET E,5,(IX+nn)
DDCBnnEB
SET E,6,(IX+nn)
DDCBnnF3
SET E,7,(IX+nn)
DDCBnnFB
H
SET H,0,(IX+nn)
DDCBnnC4
SET H,1,(IX+nn)
DDCBnnCC
SET H,2,(IX+nn)
DDCBnnD4
SET H,3,(IX+nn)
DDCBnnDC
SET H,4,(IX+nn)
DDCBnnE4
SET H,5,(IX+nn)
DDCBnnEC
SET H,6,(IX+nn)
DDCBnnF4
SET H,7,(IX+nn)
DDCBnnFC
L
SET L,0,(IX+nn)
DDCBnnC5
SET L,1,(IX+nn)
DDCBnnCD
SET L,2,(IX+nn)
DDCBnnD5
SET L,3,(IX+nn)
DDCBnnDD
SET L,4,(IX+nn)
DDCBnnE5
SET L,5,(IX+nn)
DDCBnnED
SET L,6,(IX+nn)
DDCBnnF5
SET L,7,(IX+nn)
DDCBnnFD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

3.11.8 - SET bit in (IY+d) and copy into register r

Undocumented SET bit in (IY+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official SET 0,(IY+nn) instruction sets bit 0 on a specific memory address, however the undocumented SET B,0,(IY+nn)0xFDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IY+d)_b \longleftarrow 0 \\ r \longleftarrow (IY+d)\)

76543210
11111101FD
11001011CB
d
11br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
SET A,0,(IY+nn)
FDCBnnC7
SET A,1,(IY+nn)
FDCBnnCF
SET A,2,(IY+nn)
FDCBnnD7
SET A,3,(IY+nn)
FDCBnnDF
SET A,4,(IY+nn)
FDCBnnE7
SET A,5,(IY+nn)
FDCBnnEF
SET A,6,(IY+nn)
FDCBnnF7
SET A,7,(IY+nn)
FDCBnnFF
B
SET B,0,(IY+nn)
FDCBnnC0
SET B,1,(IY+nn)
FDCBnnC8
SET B,2,(IY+nn)
FDCBnnD0
SET B,3,(IY+nn)
FDCBnnD8
SET B,4,(IY+nn)
FDCBnnE0
SET B,5,(IY+nn)
FDCBnnE8
SET B,6,(IY+nn)
FDCBnnF0
SET B,7,(IY+nn)
FDCBnnF8
C
SET C,0,(IY+nn)
FDCBnnC1
SET C,1,(IY+nn)
FDCBnnC9
SET C,2,(IY+nn)
FDCBnnD1
SET C,3,(IY+nn)
FDCBnnD9
SET C,4,(IY+nn)
FDCBnnE1
SET C,5,(IY+nn)
FDCBnnE9
SET C,6,(IY+nn)
FDCBnnF1
SET C,7,(IY+nn)
FDCBnnF9
D
SET D,0,(IY+nn)
FDCBnnC2
SET D,1,(IY+nn)
FDCBnnCA
SET D,2,(IY+nn)
FDCBnnD2
SET D,3,(IY+nn)
FDCBnnDA
SET D,4,(IY+nn)
FDCBnnE2
SET D,5,(IY+nn)
FDCBnnEA
SET D,6,(IY+nn)
FDCBnnF2
SET D,7,(IY+nn)
FDCBnnFA
E
SET E,0,(IY+nn)
FDCBnnC3
SET E,1,(IY+nn)
FDCBnnCB
SET E,2,(IY+nn)
FDCBnnD3
SET E,3,(IY+nn)
FDCBnnDB
SET E,4,(IY+nn)
FDCBnnE3
SET E,5,(IY+nn)
FDCBnnEB
SET E,6,(IY+nn)
FDCBnnF3
SET E,7,(IY+nn)
FDCBnnFB
H
SET H,0,(IY+nn)
FDCBnnC4
SET H,1,(IY+nn)
FDCBnnCC
SET H,2,(IY+nn)
FDCBnnD4
SET H,3,(IY+nn)
FDCBnnDC
SET H,4,(IY+nn)
FDCBnnE4
SET H,5,(IY+nn)
FDCBnnEC
SET H,6,(IY+nn)
FDCBnnF4
SET H,7,(IY+nn)
FDCBnnFC
L
SET L,0,(IY+nn)
FDCBnnC5
SET L,1,(IY+nn)
FDCBnnCD
SET L,2,(IY+nn)
FDCBnnD5
SET L,3,(IY+nn)
FDCBnnDD
SET L,4,(IY+nn)
FDCBnnE5
SET L,5,(IY+nn)
FDCBnnED
SET L,6,(IY+nn)
FDCBnnF5
SET L,7,(IY+nn)
FDCBnnFD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

4 - Decoding Instructions

How to decode instructions from binary

This section lists how the instructions are laid out at the bit level.

Normally if you are manually disassembling code you just need to use the list by Opcodes, however this section will be useful if you are implementing a Z80 emulator as you can see how the instruction decoding works including how the undocumented instructions work due to how the bits are organised.

How to use these decoding tables

To decode an opcode, convert it to binary then run through it from left to right, e.g. start at Bit 7 and move towards Bit 0.

As you run through the bits, start on the table from the top-left and go down then right as you find each bit. Bits are ordered with 0 first, then 1 & finally x which indicates that bit can be either 0 or 1.

When you find a match then go with that. If more than one entry matches then go for the one higher in the table as that will have higher precedence.

Z80 Instruction Decode table

To decode an instruction:

76543210
00000000 Nop
00001000 EX
0001x000 Flow
000xx111 Rotate
001xx111 Misc
00xx0001 LD Instructions
00xx0011 Arithmetic Instructions
00xx0100 Arithmetic Instructions
00xx0101 Arithmetic Instructions
00xx0110 LD Instructions
00xx1001 Arithmetic Instructions
00xxx000 Flow
00xxx010 LD Instructions
01110110 Halt
01xxxxxx LD Instructions
10xxxxxx Arithmetic Instructions
11000011 Flow
11001011 CB Prefix
11001101 Flow
11011001 EXX
1101x011 I/O
11101101 ED Prefix
1110x011 EX
11111001 LD Instructions
1111x011 Interrupts
11x01001 Flow
11x11101 DD FD Prefix
11xx0x01 Stack Instructions
11xxx000 Flow
11xxx010 Flow
11xxx100 Flow
11xxx110 Arithmetic Instructions
11xxx111 Flow

Notes:

  1. Halt 0x76 is where the invalid LD (HL),(HL) instruction would have been.

4.1 - Arithmetic Instructions

How to decode arithmetic instructions from binary

Opcodes with bits 7…5 set to 100 are the arithmetic instructions ADD, ADC, SUB and SBC. As are those starting with 7…6 set to 11 but ending with bits 2…0 set to 110. These instructions take an additional numeric operand after the opcode and use that instead of a register as the source.

Those with 7…5 set to 101 are the logic instructions AND, XOR, OR and CP.

Opcode format
76543210
 
Arithmetic with register as source, e.g. ADD A
100AFr
 
Logic with register as source, e.g. OR A
101AFr
 
8 bit number as source, e.g. SUB 5
11XAF110
n
Lookup for A and F bits
765AFInstructionr
10000 ADC r register or
110 = (HL)
1 ADD r
10 SBC r
1 SUB r
100 AND r
1 XOR r
10 OR r
1 CP r
1000 ADC n Always set to 110
1 ADD n
10 SBC n
1 SUB n
100 AND n
1 XOR n
10 OR n
1 CP n
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

4.2 - Program Flow Instructions

How to decode program flow instructions from binary
Opcode format
76543210
0001D000
e-2
 
001cc000JR
e-2
 
11000011JP
7nn0
158
 
11001001RET
 
11001101CALL
7nn0
158
 
11101001JP (HL)
 
11ccc000RET
 
11ccc010JP
7nn0
158
 
11ccc100CALL
7nn0
158
 
11b111RST
Conditions
cccccAbbrev Condition Flag
00000NZ Non Zero Z
01001Z Zero
10010NC No Carry C
11011C Carry
 100 PO Parity Odd P/V
101 PE Parity Even
110 P Sign Positive S
111 M Sign Negative
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111
D
InstructionD
DJNZ0
JR1

4.3 - Increment Decrement Instructions

How to decode increment and decrement instructions from binary
Opcode format
76543210
 
00XXD01116-bit
 
00r10D8-bit
 
(IX+d) or (IY+d)
11Z11101DD or FD prefix
0011010D
d
 
IX or IY
11Z11101DD or FD prefix
0010D011
7nn0
158
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
XX Register
InstructionXX
BC00
DE01
HL10
A11
D direction
DirectionD
INC0
DEC1
Z
RegisterZ
IX0
IY1

4.4 - LD Load instructions

How to decode ld instructions from binary
Opcode format
76543210
 
Set 1
000B010
 
Set 4
00B0001
 
Set 2
001B010
7nn0
158
 
Set 3
00b110
n
 
LD r, r'
01rr'
 
LD r, (HL)
01r110
 
LD SP,HL
11111001
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
ValuebB
000000
100101
201010
301111
4100
5101
6110
7111
Set 1 store a in memory
43Instruction
00 LD (BC),A
1 LD (DE),A
10 LD A,(BC)
1 LD A,(DE)
Set 2 store in memory
54Instruction
00 LD (nn),HL
1 LD (nn),A
10 LD HL,(nn)
1 LD A,(nn)
Set 3 set to constant n
432Instruction
000 LD B,n
1 LD C,n
10 LD D,n
1 LD E,n
100 LD H,n
1 LD L,n
10 LD (HL),n
1 LD A,n
Set 4 set to constant nnn
54Instruction
00 LD BC,nn
1 LD DE,nn
10 LD HL,nn
1 LD SP,nn

4.5 - Miscelaneous Instructions

How to decode IO, EX and Interrupt instructions from binary

Only four rotate instructions are defined in the main opcode set, all the rest require the CB prefix.

Opcode format
76543210
 
IO
1101D011
 
EXX
11011001
 
EX
1110W011
 
Interrupts
1111E011
D I/O Direction
InstructionD
Out0
In1
W EX registers
InstructionW
DE_HL0
(SP)_HL1
E Interrupt Enable
InstructionE
DI0
EI1

4.6 - Rotate Instructions

How to decode rotate instructions from binary

Only four rotate instructions are defined in the main opcode set, all the rest require the CB prefix.

Opcode format
76543210
000FD111
 
00000111RLCA
00010111RLA
00000111RRCA
00011111RRA
F Carry Flag
InstructionF
With Carry0
Without Carry1
D Direction
InstructionD
Left0
Right1

4.7 - Decoding CB Prefix

How the CB instruction prefix works

Instructions with the CB prefix consist of instructions that manipulate individual bits in a register or memory.

76543210
00000xxx RLC r
00001xxx RRC r
00010xxx RL
00011xxx RR
00100xxx SLA
00101xxx SRA
00110xxx SLL
00111xxx SRL
01xxxxxx BIT b,r
10xxxxxx RES b,r
11xxxxxx SET b,r

Operations with IX and IY registers

The operations here which operator on the (HL) register do also support use with the IX and IY registers with a relative offset. They are identical to the (HL) operation but with a DD or FD prefix.

Only instructions with the lower nibble set to 6 or E are documented. The other opcodes are undocumented.

Undocumented SLL instruction

Op codes CB30CB37 are undocumented; but they do perform a shift left operation, placing a 1 in bit 0 and setting the carry flag to the original bit 7.

4.8 - Decoding ED Prefix

How the ED instruction prefix works

Instructions with the ED prefix consist of instructions that are not used as often as those in the main group.

76543210
01000100 NEG
01000101 RETN
01001101 RETI
01010011
01011110 IM2
010x0110 IMx
010x0111 LD
010x1000 LD
01100111 RRD (HL)
01101000 LD
01101111 RLD (HL)
01110001
01111001 OUT (C) A
01xx0010 SBC
01xx1010 ADC
01xxx000 IN r (C)
01xxx001 OUT (C) r
01xxx011 LD
101xx00x Block Memory
101xx01x Block IO

4.9 - Decoding DD and FD Prefixes

How the DD and FD instruction prefixes work

Instructions with either the DD or FD prefixes affect those instructions that operate against the memory addressed by HL, changing them to use either the IX or IY registers with an offset.

Instructions that refer directly to the HL register will then act directly against either IX or IY. For those that refer to (HL), i.e. the memory pointed to by HL then the instructions use an additional relative offset that's added to either the IX or IY registers, and are written as (IX+d) or (IY+d).

Instructions with the DD prefix use the IX register, whilst the FD prefix uses the IY register.

DDCB and FDCB Prefixes

The DD and FD prefixes extends though the CB prefix as it does for normal instructions. Just like the CB prefix

The format of the instruction also changes slightly as they change the behaviour of the existing instructions with the CB prefix. These instructions are all four bytes long with the third byte consisting of the offset.

For example: The RLC (HL) is encoded as CB06.

With the DD prefix this becomes RLC (IX+d) but the instruction is formatted as DDCBdd06. With the FD prefix this becomes RLC (IY+d), formatted as FDCBdd06.

Note that the offset d is before the final part of the operand, not after as you might expect.

Decoder

All of these have either DD or FD as the previous prefix byte and a displacement immediately after them.

76543210
00100001 LD
0010X011 INC DEC
0010xx10 LD
0011010D IncDec
00110110 LD
00xx1001 ADD
0100010x INC DEC
01110110
01110xxx LD
01xxx110 LD
10xx0110 LD
11001011 CB Prefix
11100011 EX
11100x01 Stack Instructions
11101001 Flow
11111001 LD

5 - Optimizing code

Things to try to optimise Z80 code

Writing code on an 8-bit microcomputer requires a skill that has been lost in the modern programming era. These days, developers are used to having Gigabytes of memory and processors that run at multiple Gigahertz.

In the microcomputer era we had far, far less resources. Processor clocks ran at 2 or 4 MHz, one thousandth of the clock speed of modern processors. If we were lucky we had 32K, 48K or 64K of memory to play with and that was it.

Because of this, we had to learn pretty quickly how to optimise our code to fit into memory. If we were lucky we could use a floppy disk to page in parts of the program as needed, but even then when a Cassette tape was the primary medium for a platform that wasn't even possible.

Optimisations at the machine code level would be a balance of reducing the size of code and having code run as fast as possible.

Sometimes you might sacrifice some memory for speed if the routine is important, for example it's doing a transform for some graphics in real time, but most of the time it's to reduce the memory used.

5.1 - Accumulator

Optimising use of the A register

Setting the Accumulator to 0

When dealing with loading 0 into the Accumulator, there's several ways to do it.

3E00LDA,0Traditional way to set A to 0
AFXORAAnything xor itself is 0
97SUBAA-A=0

The downside to the above options is that they also affect the flags. However, they are only 1 byte long not 2 and are both 3 T-states faster.

Inverting A

If inverting A, i.e. swapping each bit from 1 to 0 and vis-versa then instead of XOR 0xFF use CPL instead. It's both faster, 1 byte and that's all that instruction does.

EEFFXOR0xFFA=A XOR 0xff
2FCPLThis instruction does exactly the same thing and nothing else!

The downside is that CPL does not affect the flags whilst XOR does.

5.2 - Comparisons

Optimising comparing numbers

A = 0

A common test is to see if A is 0, so you would expect to use CP 0 to test for it.

Just like setting A to 0 we can compare quicker. In this case, instead of CP 0 we can just use either OR A or AND A instead. Just 1 byte and 3 T-states faster.

FE00CP0A-0 will set Z if A is also 0
A7ANDAAnything AND itself is itself but Z is set if A is 0
B7ORAAnything OR itself is itself but Z is set if A is 0

For example, take this simple routine which writes a NULL terminated string pointed to by HL to the screen of the Sinclair ZX Spectrum:

Print null terminated string at HL to the screen
printStrLDA,(HL)get next byte
CP0check for null
RETZStop when we get a null
RST2print the character
INCHLmove to next character
JRprintStrloop back

The optimisation here is to replace CP 0 with OR A

Print null terminated string at HL to the screen
printStrLDA,(HL)get next byte
ORAcheck for null
RETZStop when we get a null
RST2print the character
INCHLmove to next character
JRprintStrloop back

A = 1

Comparing A to 1 can also be done using DEC A instead of CP 1. By decrementing A, the Z flag will be set if A is now 0. Like above its faster and 1 byte, but it also alters A, so it's not really of any use unless you don't care about the value of A after the test.

FE01CP1A-1 will set Z if A is also 1
3DDECAA=A-1, Z is set if A is now 0

Internally, CP 1 just does A-1 but discards the result which is why DEC A works in this instance.

Compare number

With CP it's easy to test for less than (<), equals (=), not equals (!=) or greater-than-equals (>=) because of how the C and Z flags are used:

CP15test A against 15
RETCReturn if A < 15
RETNCReturn if A >= 15
RETZReturn if A = 15
RETNZReturn if A != 15

The following shows how to get the other two tests, Less-Than-Equals (<=) and Greater-Than(>):

A <= n

This is a simple one. As CP tests against A-n then if A=N then Z is set but if A < n then C is set.

CP15test for A<=15
RETCReturn if A<15
RETZReturn if A=15

To optimise this we should test against n+1 instead. Doing this means we can just use the Carry flag as it would be set when A < n+1:

CP15+1test for A<16
RETCReturn if A<16

A > n

This is the opposite problem. Here Carry is clear when A>=n, so to get A>n we first need to test for equals using the Z flag and if that's not set then check for the Carry flag to be clear:

CP15test for A>15
JRZ, skipSkip if A=15
RETNCReturn if A>=15
skipContinue as A was <= 15

Like the previous example, this can be optimised simply by adding 1 and then testing for A >= (n+1) instead:

CP15+1test for A>=16
RETNCReturn if A>=16

Wasteful use of CP

It's easy to forget that some instructions set the flags based on the result so frequently you do not need to use CP to test for a condition when the result is already known:

Here we check for bit 1 of A is set and if it is we exit the subroutine:

E601AND1A=A AND 0x01
FE01CP1Is A set to 1
C8RETZReturn is A is now 1

Here the CP isn't required as AND will set Z if A=0, so we can remove the CP and use NZ instead saving 2 bytes:

E601AND1A=A AND 0x01
C8RETNZReturn as A is now 1

Testing bits

Testing Bit 0 of A

The standard method of testing if bit 0 of A is set is to use BIT 0,A:

CB47BIT0,ATest if BIT 0 is set
C8RETNZReturn as bit 0 of A was set

If we don't need A afterwards then we can optimise this by using a right shift instead:

1FRRAShift A right 1 bit, C=original bit 0
C8RETCReturn as bit 0 of A was set

This works as we just shifted bit 0 into the Carry Flag and we save an additional byte in the process.

Using RRA would be faster & saves 1 byte, but it destroys A. If you need to keep A intact then keep the BIT instruction.

Testing Bit 7 of A

Just like testing bit 0, with bit 7 we can do the same but shifting right instead. So rather than using BIT 7,A like:

CB7FBIT7,ATest if BIT 7 is set
C8RETNZReturn as bit 7 of A was set

We can just use RLA and test the Carry flag:

17RLAShift A left 1 bit, C=original bit 7
C8RETCReturn as bit 7 of A was set

The downside of this is it destroys the contents of A.

5.3 - Math

Optimising mathematics

Basic Arithmetic

A=-B

A simple one, we want to set A to be -B.

The logical way is to load A with B then negate it:

78LDA,BSet A to B
ED44NEGNegate A to get A=-B

But a quicker and shorter way is:

AFXORAA=0
90SUBBA=0-B = -B

5.4 - Bit Shifting

Optimising bit shifting

Bit shifting, be it rotating left or right is so common it's easy to create slow code if you are not careful.

Shift BC, DE or HL left one bit

This is a 16 bit shift left operation. The first thought would be, especially if you have a 6502 background like myself, is to shift L left 1 bit, clearing bit 0 with carry set to the original bit 7 state, then shift H left 1 bit pulling in carry into bit 0:

CB25SLALShift L left, set bit 0 to 0
CB14RLHShift H left, set bit 0 to original bit 7 from L

However any shift left operation is the same as multiplying the value by 2 or just adding to itself, and the Z80 has a single byte operation to do this.

29ADDHL,HLShift HL left 1 bit

The same applies for BC or DE. If you need to shift a 16-bit register left one bit then always use ADD.

Shift 8-bit register left one bit

This might seem odd but the same optimisation can be done for any of the 8-bit registers. You can either use SLA or you can just add the register to itself.

Shift A left one bit, set bit 0 to 0
CB27SLAA2 bytes 8 t-states
87ADDA,A1 byte 4 t-states

Here we can halve both the code size and the time taken to perform the shift.

The downside with ADD is that the original bit 7 of the register is lost. SLA will preserve it in the Carry flag.

Other than that it's identical, with Z set if the register is now 0 and S set if the new bit 7 is set.

6 - reference

6.1 - Instruction List by name

ADC A,(HL)8E
ADC A,(IX+d)DD8Enn
ADC A,(IY+d)FD8Enn
ADC A,A8F
ADC A,B88
ADC A,C89
ADC A,D8A
ADC A,E8B
ADC A,H8C
ADC A,IXhDD8C
ADC A,IXlDD8D
ADC A,IYhFD8C
ADC A,IYlFD8D
ADC A,L8D
ADC A,nCEnn
ADC HL,BCED4Ann
ADC HL,DEED5Ann
ADC HL,HLED6Ann
ADC HL,SPED7Ann
ADD A,(HL)86
ADD A,(IX+d)DD86nn
ADD A,(IY+d)FD86nn
ADD A,A87
ADD A,B80
ADD A,C81
ADD A,D82
ADD A,E83
ADD A,H84
ADD A,IXhDD84
ADD A,IXlDD85
ADD A,IYhFD84
ADD A,IYlFD85
ADD A,L85
ADD A,nC6nn
ADD HL,BC09
ADD HL,DE19
ADD HL,HL29
ADD HL,SP39
ADD IX,BCDD09nn
ADD IX,DEDD19nn
ADD IX,IXDD29nn
ADD IX,SPDD39nn
ADD IY,BCFD09nn
ADD IY,DEFD19nn
ADD IY,IYFD29nn
ADD IY,SPFD39nn
AND A,(HL)A6
AND A,(IX+d)DDA6nn
AND A,(IY+d)FDA6nn
AND A,AA7
AND A,BA0
AND A,CA1
AND A,DA2
AND A,EA3
AND A,HA4
AND A,LA5
AND A,nE6nn
AND IXhDDA4
AND IXlDDA5
AND IYhFDA4
AND IYlFDA5
BIT 0,(HL)CB46nn
BIT 0,(IX+d)DDCBnn40
BIT 0,(IX+d)DDCBnn41
BIT 0,(IX+d)DDCBnn42
BIT 0,(IX+d)DDCBnn43
BIT 0,(IX+d)DDCBnn44
BIT 0,(IX+d)DDCBnn45
BIT 0,(IX+d)DDCBnn46
BIT 0,(IX+d)DDCBnn47
BIT 0,(IY+d)FDCBnn40
BIT 0,(IY+d)FDCBnn41
BIT 0,(IY+d)FDCBnn42
BIT 0,(IY+d)FDCBnn43
BIT 0,(IY+d)FDCBnn44
BIT 0,(IY+d)FDCBnn45
BIT 0,(IY+d)FDCBnn46
BIT 0,(IY+d)FDCBnn47
BIT 0,ACB47nn
BIT 0,BCB40nn
BIT 0,CCB41nn
BIT 0,DCB42nn
BIT 0,ECB43nn
BIT 0,HCB44nn
BIT 0,LCB45nn
BIT 1,(HL)CB4Enn
BIT 1,(IX+d)DDCBnn48
BIT 1,(IX+d)DDCBnn49
BIT 1,(IX+d)DDCBnn4A
BIT 1,(IX+d)DDCBnn4B
BIT 1,(IX+d)DDCBnn4C
BIT 1,(IX+d)DDCBnn4D
BIT 1,(IX+d)DDCBnn4E
BIT 1,(IX+d)DDCBnn4F
BIT 1,(IY+d)FDCBnn48
BIT 1,(IY+d)FDCBnn49
BIT 1,(IY+d)FDCBnn4A
BIT 1,(IY+d)FDCBnn4B
BIT 1,(IY+d)FDCBnn4C
BIT 1,(IY+d)FDCBnn4D
BIT 1,(IY+d)FDCBnn4E
BIT 1,(IY+d)FDCBnn4F
BIT 1,ACB4Fnn
BIT 1,BCB48nn
BIT 1,CCB49nn
BIT 1,DCB4Ann
BIT 1,ECB4Bnn
BIT 1,HCB4Cnn
BIT 1,LCB4Dnn
BIT 2,(HL)CB56nn
BIT 2,(IX+d)DDCBnn50
BIT 2,(IX+d)DDCBnn51
BIT 2,(IX+d)DDCBnn52
BIT 2,(IX+d)DDCBnn53
BIT 2,(IX+d)DDCBnn54
BIT 2,(IX+d)DDCBnn55
BIT 2,(IX+d)DDCBnn56
BIT 2,(IX+d)DDCBnn57
BIT 2,(IY+d)FDCBnn50
BIT 2,(IY+d)FDCBnn51
BIT 2,(IY+d)FDCBnn52
BIT 2,(IY+d)FDCBnn53
BIT 2,(IY+d)FDCBnn54
BIT 2,(IY+d)FDCBnn55
BIT 2,(IY+d)FDCBnn56
BIT 2,(IY+d)FDCBnn57
BIT 2,ACB57nn
BIT 2,BCB50nn
BIT 2,CCB51nn
BIT 2,DCB52nn
BIT 2,ECB53nn
BIT 2,HCB54nn
BIT 2,LCB55nn
BIT 3,(HL)CB5Enn
BIT 3,(IX+d)DDCBnn58
BIT 3,(IX+d)DDCBnn59
BIT 3,(IX+d)DDCBnn5A
BIT 3,(IX+d)DDCBnn5B
BIT 3,(IX+d)DDCBnn5C
BIT 3,(IX+d)DDCBnn5D
BIT 3,(IX+d)DDCBnn5E
BIT 3,(IX+d)DDCBnn5F
BIT 3,(IY+d)FDCBnn58
BIT 3,(IY+d)FDCBnn59
BIT 3,(IY+d)FDCBnn5A
BIT 3,(IY+d)FDCBnn5B
BIT 3,(IY+d)FDCBnn5C
BIT 3,(IY+d)FDCBnn5D
BIT 3,(IY+d)FDCBnn5E
BIT 3,(IY+d)FDCBnn5F
BIT 3,ACB5Fnn
BIT 3,BCB58nn
BIT 3,CCB59nn
BIT 3,DCB5Ann
BIT 3,ECB5Bnn
BIT 3,HCB5Cnn
BIT 3,LCB5Dnn
BIT 4,(HL)CB66nn
BIT 4,(IX+d)DDCBnn60
BIT 4,(IX+d)DDCBnn61
BIT 4,(IX+d)DDCBnn62
BIT 4,(IX+d)DDCBnn63
BIT 4,(IX+d)DDCBnn64
BIT 4,(IX+d)DDCBnn65
BIT 4,(IX+d)DDCBnn66
BIT 4,(IX+d)DDCBnn67
BIT 4,(IY+d)FDCBnn60
BIT 4,(IY+d)FDCBnn61
BIT 4,(IY+d)FDCBnn62
BIT 4,(IY+d)FDCBnn63
BIT 4,(IY+d)FDCBnn64
BIT 4,(IY+d)FDCBnn65
BIT 4,(IY+d)FDCBnn66
BIT 4,(IY+d)FDCBnn67
BIT 4,ACB67nn
BIT 4,BCB60nn
BIT 4,CCB61nn
BIT 4,DCB62nn
BIT 4,ECB63nn
BIT 4,HCB64nn
BIT 4,LCB65nn
BIT 5,(HL)CB6Enn
BIT 5,(IX+d)DDCBnn68
BIT 5,(IX+d)DDCBnn69
BIT 5,(IX+d)DDCBnn6A
BIT 5,(IX+d)DDCBnn6B
BIT 5,(IX+d)DDCBnn6C
BIT 5,(IX+d)DDCBnn6D
BIT 5,(IX+d)DDCBnn6E
BIT 5,(IX+d)DDCBnn6F
BIT 5,(IY+d)FDCBnn68
BIT 5,(IY+d)FDCBnn69
BIT 5,(IY+d)FDCBnn6A
BIT 5,(IY+d)FDCBnn6B
BIT 5,(IY+d)FDCBnn6C
BIT 5,(IY+d)FDCBnn6D
BIT 5,(IY+d)FDCBnn6E
BIT 5,(IY+d)FDCBnn6F
BIT 5,ACB6Fnn
BIT 5,BCB68nn
BIT 5,CCB69nn
BIT 5,DCB6Ann
BIT 5,ECB6Bnn
BIT 5,HCB6Cnn
BIT 5,LCB6Dnn
BIT 6,(HL)CB76nn
BIT 6,(IX+d)DDCBnn70
BIT 6,(IX+d)DDCBnn71
BIT 6,(IX+d)DDCBnn72
BIT 6,(IX+d)DDCBnn73
BIT 6,(IX+d)DDCBnn74
BIT 6,(IX+d)DDCBnn75
BIT 6,(IX+d)DDCBnn76
BIT 6,(IX+d)DDCBnn77
BIT 6,(IY+d)FDCBnn70
BIT 6,(IY+d)FDCBnn71
BIT 6,(IY+d)FDCBnn72
BIT 6,(IY+d)FDCBnn73
BIT 6,(IY+d)FDCBnn74
BIT 6,(IY+d)FDCBnn75
BIT 6,(IY+d)FDCBnn76
BIT 6,(IY+d)FDCBnn77
BIT 6,ACB77nn
BIT 6,BCB70nn
BIT 6,CCB71nn
BIT 6,DCB72nn
BIT 6,ECB73nn
BIT 6,HCB74nn
BIT 6,LCB75nn
BIT 7,(HL)CB7Enn
BIT 7,(IX+d)DDCBnn78
BIT 7,(IX+d)DDCBnn79
BIT 7,(IX+d)DDCBnn7A
BIT 7,(IX+d)DDCBnn7B
BIT 7,(IX+d)DDCBnn7C
BIT 7,(IX+d)DDCBnn7D
BIT 7,(IX+d)DDCBnn7E
BIT 7,(IX+d)DDCBnn7F
BIT 7,(IY+d)FDCBnn78
BIT 7,(IY+d)FDCBnn79
BIT 7,(IY+d)FDCBnn7A
BIT 7,(IY+d)FDCBnn7B
BIT 7,(IY+d)FDCBnn7C
BIT 7,(IY+d)FDCBnn7D
BIT 7,(IY+d)FDCBnn7E
BIT 7,(IY+d)FDCBnn7F
BIT 7,ACB7Fnn
BIT 7,BCB78nn
BIT 7,CCB79nn
BIT 7,DCB7Ann
BIT 7,ECB7Bnn
BIT 7,HCB7Cnn
BIT 7,LCB7Dnn
CALL C,nnDCnnnn
CALL N,nnFCnnnn
CALL NC,nnD4nnnn
CALL NZ,nnC4nnnn
CALL P,nnF4nnnn
CALL PE,nnECnnnn
CALL PO,nnE4nnnn
CALL Z,nnCCnnnn
CALL nnCDnnnn
CCF3F
CCF3F
CP (HL)BE
CP (IX+d)DDBEnn
CP (IY+d)FDBEnn
CP ABF
CP BB8
CP CB9
CP DBA
CP EBB
CP HBC
CP IXhDDBC
CP IXlDDBD
CP IYhFDBC
CP IYlFDBD
CP LBD
CP nFEnn
CPDEDA9nn
CPDREDB9nn
CPIEDA1nn
CPIREDB1nn
CPL2F
CPL2F
DAA27
DEC (HL)35
DEC (IX+d)DD35nn
DEC (IY+d)FD35nn
DEC A3D
DEC B05
DEC BC0B
DEC C0D
DEC D15
DEC DE1B
DEC E1D
DEC H25
DEC HL2B
DEC IXDD2Bnn
DEC IXhDD25
DEC IXlDD2D
DEC IYFD2Bnn
DEC IYhFD25
DEC IYlFD2D
DEC L2D
DEC SP3B
DIF3
DJNZ e10nn
EIFB
EX (SP), HLE3
EX (SP), IXDDE3nn
EX (SP), IYFDE3nn
EX AF, AF'08
EX DE, HLEB
EXXD9
HALT76
IM0ED46nn
IM1ED56nn
IM2ED5Enn
IN A,(C)ED7Bnn
IN A,(n)DBnn
IN B,(C)ED40nn
IN C,(C)ED48nn
IN D,(C)ED50nn
IN E,(C)ED58nn
IN F,(C)ED70nn
IN H,(C)ED60nn
IN L,(C)ED68nn
INC (HL)34
INC (IX+d)DD34nn
INC (IY+d)FD34nn
INC A3C
INC B04
INC BC03
INC C0C
INC D14
INC DE13
INC E1C
INC H24
INC HL23
INC IXDD23nn
INC IXhDD24
INC IXlDD2C
INC IYFD23nn
INC IYhFD24
INC IYlFD2C
INC L2C
INC SP33
INDEDAAnn
INDREDBAnn
INIEDA2nn
INIREDB2nn
JP (HL)E9
JP (IX)DDE9nn
JP (IY)FDE9nn
JP C,nnDAnnnn
JP N,nnFAnnnn
JP NC,nnD2nnnn
JP NZ,nnC2nnnn
JP P,nnF2nnnn
JP PE,nnEAnnnn
JP PO,nnE2nnnn
JP Z,nnCAnnnn
JP nnC3nnnn
JR C,e38nn
JR NC,e30nn
JR NZ,e20nn
JR Z,e28nn
JR e18nn
LD (BC), A02
LD (DE), A12
LD (HL), A77
LD (HL), B70
LD (HL), C71
LD (HL), D72
LD (HL), E73
LD (HL), H74
LD (HL), L75
LD (HL), n36nn
LD (IX+d), ADD77nn
LD (IX+d), BDD70nn
LD (IX+d), CDD71nn
LD (IX+d), DDD72nn
LD (IX+d), EDD73nn
LD (IX+d), HDD74nn
LD (IX+d), LDD75nn
LD (IX+d), nDD36nnnn
LD (IY+d), AFD77nn
LD (IY+d), BFD70nn
LD (IY+d), CFD71nn
LD (IY+d), DFD72nn
LD (IY+d), EFD73nn
LD (IY+d), HFD74nn
LD (IY+d), LFD75nn
LD (IY+d), nFD36nnnn
LD (nn), A32nnnn
LD (nn), BCED43nnnn
LD (nn), DEED53nnnn
LD (nn), HL22nnnn
LD (nn), HLED63nnnn
LD (nn), IXDD22nnnn
LD (nn), IYFD22nnnn
LD (nn), SPED73nnnn
LD A, (BC)0A
LD A, (DE)1A
LD A, (HL)7E
LD A, (IX+d)DD7Enn
LD A, (IY+d)FD7Enn
LD A, (nn)3Annnn
LD A, A7F
LD A, B78
LD A, C79
LD A, D7A
LD A, E7B
LD A, H7C
LD A, IED57nn
LD A, L7D
LD A, RED5Fnn
LD A, n3Enn
LD A,IXhDD7C
LD A,IXlDD7D
LD A,IYhFD7C
LD A,IYlFD7D
LD B, (HL)46
LD B, (IX+d)DD46nn
LD B, (IY+d)FD46nn
LD B, A47
LD B, B40
LD B, C41
LD B, D42
LD B, E43
LD B, H44
LD B, L45
LD B, n06nn
LD B,IXhDD44
LD B,IXlDD45
LD B,IYhFD44
LD B,IYlFD45
LD BC, (nn)ED4Bnnnn
LD BC, nn01nnnn
LD C, (HL)4E
LD C, (IX+d)DD4Enn
LD C, (IY+d)FD4Enn
LD C, A4F
LD C, B48
LD C, C49
LD C, D4A
LD C, E4B
LD C, H4C
LD C, L4D
LD C, n0Enn
LD C,IXhDD4C
LD C,IXlDD4D
LD C,IYhFD4C
LD C,IYlFD4D
LD D, (HL)56
LD D, (IX+d)DD56nn
LD D, (IY+d)FD56nn
LD D, A57
LD D, B50
LD D, C51
LD D, D52
LD D, E53
LD D, H54
LD D, L55
LD D, n16nn
LD D,IXhDD54
LD D,IXlDD55
LD D,IYhFD54
LD D,IYlFD55
LD DE, (nn)ED5Bnnnn
LD DE, nn11nnnn
LD E, (HL)5E
LD E, (IX+d)DD5Enn
LD E, (IY+d)FD5Enn
LD E, A5F
LD E, B58
LD E, C59
LD E, D5A
LD E, E5B
LD E, H5C
LD E, L5D
LD E, n1Enn
LD E,IXhDD5C
LD E,IXlDD5D
LD E,IYhFD5C
LD E,IYlFD5D
LD H, (HL)66
LD H, (IX+d)DD66nn
LD H, (IY+d)FD66nn
LD H, A67
LD H, B60
LD H, C61
LD H, D62
LD H, E63
LD H, H64
LD H, L65
LD H, n26nn
LD HL, (nn)2Annnn
LD HL, (nn)ED6Bnnnn
LD HL, nn21nnnn
LD I, AED47nn
LD IX, (nn)DD2Annnn
LD IX, nnDD21nnnn
LD IXh,ADD67
LD IXh,BDD60
LD IXh,CDD61
LD IXh,DDD62
LD IXh,EDD63
LD IXh,IHhDD64
LD IXh,IHlDD65
LD IXh,nDD26nn
LD IXl,ADD6F
LD IXl,BDD68
LD IXl,CDD69
LD IXl,DDD6A
LD IXl,EDD6B
LD IXl,IHhDD6C
LD IXl,IHlDD6D
LD IXl,nDD2Enn
LD IY, (nn)FD2Annnn
LD IY, nnFD21nnnn
LD IYh,AFD67
LD IYh,BFD60
LD IYh,CFD61
LD IYh,DFD62
LD IYh,EFD63
LD IYh,IHhFD64
LD IYh,IHlFD65
LD IYh,nFD26nn
LD IYl,AFD6F
LD IYl,BFD68
LD IYl,CFD69
LD IYl,DFD6A
LD IYl,EFD6B
LD IYl,IHhFD6C
LD IYl,IHlFD6D
LD IYl,nFD2Enn
LD L, (HL)6E
LD L, (IX+d)DD6Enn
LD L, (IY+d)FD6Enn
LD L, A6F
LD L, B68
LD L, C69
LD L, D6A
LD L, E6B
LD L, H6C
LD L, L6D
LD L, n2Enn
LD R, AED4Fnn
LD SP, (nn)ED7Bnnnn
LD SP, HLF9
LD SP, IXDDF9nn
LD SP, IYFDF9nn
LD SP, nn31nnnn
LDDEDA8nn
LDDREDB8nn
LDIEDA0nn
LDIREDB0nn
NEGED44nn
NEGED44nn
NOP00
OR A,(HL)B6
OR A,(IX+d)DDB6nn
OR A,(IY+d)FDB6nn
OR A,AB7
OR A,BB0
OR A,CB1
OR A,DB2
OR A,EB3
OR A,HB4
OR A,LB5
OR A,nF6nn
OR IXhDDB4
OR IXlDDB5
OR IYhFDB4
OR IYlFDB5
OUT (C),AED79nn
OUT (C),BED41nn
OUT (C),CED49nn
OUT (C),DED51nn
OUT (C),EED59nn
OUT (C),FED71nn
OUT (C),HED61nn
OUT (C),LED69nn
OUT (n),AD3nn
OUTDEDABnn
OUTDREDBBnn
OUTIEDA3nn
OUTIREDB3nn
POP AFF1
POP BCC1
POP DED1
POP HLE1
POP IXDDE1nn
POP IYFDE1nn
PUSH AFF5
PUSH BCC5
PUSH DED5
PUSH HLE5
PUSH IXDDE5nn
PUSH IYFDE5nn
RES 0,(HL)CB86nn
RES 0,(IX+d)DDCBnn86
RES 0,(IY+d)FDCBnn86
RES 0,ACB87nn
RES 0,BCB80nn
RES 0,CCB81nn
RES 0,DCB82nn
RES 0,ECB83nn
RES 0,HCB84nn
RES 0,LCB85nn
RES 1,(HL)CB8Enn
RES 1,(IX+d)DDCBnn8E
RES 1,(IY+d)FDCBnn8E
RES 1,ACB8Fnn
RES 1,BCB88nn
RES 1,CCB89nn
RES 1,DCB8Ann
RES 1,ECB8Bnn
RES 1,HCB8Cnn
RES 1,LCB8Dnn
RES 2,(HL)CB96nn
RES 2,(IX+d)DDCBnn96
RES 2,(IY+d)FDCBnn96
RES 2,ACB97nn
RES 2,BCB90nn
RES 2,CCB91nn
RES 2,DCB92nn
RES 2,ECB93nn
RES 2,HCB94nn
RES 2,LCB95nn
RES 3,(HL)CB9Enn
RES 3,(IX+d)DDCBnn9E
RES 3,(IY+d)FDCBnn9E
RES 3,ACB9Fnn
RES 3,BCB98nn
RES 3,CCB99nn
RES 3,DCB9Ann
RES 3,ECB9Bnn
RES 3,HCB9Cnn
RES 3,LCB9Dnn
RES 4,(HL)CBA6nn
RES 4,(IX+d)DDCBnnA6
RES 4,(IY+d)FDCBnnA6
RES 4,ACBA7nn
RES 4,BCBA0nn
RES 4,CCBA1nn
RES 4,DCBA2nn
RES 4,ECBA3nn
RES 4,HCBA4nn
RES 4,LCBA5nn
RES 5,(HL)CBAEnn
RES 5,(IX+d)DDCBnnAE
RES 5,(IY+d)FDCBnnAE
RES 5,ACBAFnn
RES 5,BCBA8nn
RES 5,CCBA9nn
RES 5,DCBAAnn
RES 5,ECBABnn
RES 5,HCBACnn
RES 5,LCBADnn
RES 6,(HL)CBB6nn
RES 6,(IX+d)DDCBnnB6
RES 6,(IY+d)FDCBnnB6
RES 6,ACBB7nn
RES 6,BCBB0nn
RES 6,CCBB1nn
RES 6,DCBB2nn
RES 6,ECBB3nn
RES 6,HCBB4nn
RES 6,LCBB5nn
RES 7,(HL)CBBEnn
RES 7,(IX+d)DDCBnnBE
RES 7,(IY+d)FDCBnnBE
RES 7,ACBBFnn
RES 7,BCBB8nn
RES 7,CCBB9nn
RES 7,DCBBAnn
RES 7,ECBBBnn
RES 7,HCBBCnn
RES 7,LCBBDnn
RES A,0,(IX+nn)DDCBnn87
RES A,0,(IY+nn)FDCBnn87
RES A,1,(IX+nn)DDCBnn8F
RES A,1,(IY+nn)FDCBnn8F
RES A,2,(IX+nn)DDCBnn97
RES A,2,(IY+nn)FDCBnn97
RES A,3,(IX+nn)DDCBnn9F
RES A,3,(IY+nn)FDCBnn9F
RES A,4,(IX+nn)DDCBnnA7
RES A,4,(IY+nn)FDCBnnA7
RES A,5,(IX+nn)DDCBnnAF
RES A,5,(IY+nn)FDCBnnAF
RES A,6,(IX+nn)DDCBnnB7
RES A,6,(IY+nn)FDCBnnB7
RES A,7,(IX+nn)DDCBnnBF
RES A,7,(IY+nn)FDCBnnBF
RES B,0,(IX+nn)DDCBnn80
RES B,0,(IY+nn)FDCBnn80
RES B,1,(IX+nn)DDCBnn88
RES B,1,(IY+nn)FDCBnn88
RES B,2,(IX+nn)DDCBnn90
RES B,2,(IY+nn)FDCBnn90
RES B,3,(IX+nn)DDCBnn98
RES B,3,(IY+nn)FDCBnn98
RES B,4,(IX+nn)DDCBnnA0
RES B,4,(IY+nn)FDCBnnA0
RES B,5,(IX+nn)DDCBnnA8
RES B,5,(IY+nn)FDCBnnA8
RES B,6,(IX+nn)DDCBnnB0
RES B,6,(IY+nn)FDCBnnB0
RES B,7,(IX+nn)DDCBnnB8
RES B,7,(IY+nn)FDCBnnB8
RES C,0,(IX+nn)DDCBnn81
RES C,0,(IY+nn)FDCBnn81
RES C,1,(IX+nn)DDCBnn89
RES C,1,(IY+nn)FDCBnn89
RES C,2,(IX+nn)DDCBnn91
RES C,2,(IY+nn)FDCBnn91
RES C,3,(IX+nn)DDCBnn99
RES C,3,(IY+nn)FDCBnn99
RES C,4,(IX+nn)DDCBnnA1
RES C,4,(IY+nn)FDCBnnA1
RES C,5,(IX+nn)DDCBnnA9
RES C,5,(IY+nn)FDCBnnA9
RES C,6,(IX+nn)DDCBnnB1
RES C,6,(IY+nn)FDCBnnB1
RES C,7,(IX+nn)DDCBnnB9
RES C,7,(IY+nn)FDCBnnB9
RES D,0,(IX+nn)DDCBnn82
RES D,0,(IY+nn)FDCBnn82
RES D,1,(IX+nn)DDCBnn8A
RES D,1,(IY+nn)FDCBnn8A
RES D,2,(IX+nn)DDCBnn92
RES D,2,(IY+nn)FDCBnn92
RES D,3,(IX+nn)DDCBnn9A
RES D,3,(IY+nn)FDCBnn9A
RES D,4,(IX+nn)DDCBnnA2
RES D,4,(IY+nn)FDCBnnA2
RES D,5,(IX+nn)DDCBnnAA
RES D,5,(IY+nn)FDCBnnAA
RES D,6,(IX+nn)DDCBnnB2
RES D,6,(IY+nn)FDCBnnB2
RES D,7,(IX+nn)DDCBnnBA
RES D,7,(IY+nn)FDCBnnBA
RES E,0,(IX+nn)DDCBnn83
RES E,0,(IY+nn)FDCBnn83
RES E,1,(IX+nn)DDCBnn8B
RES E,1,(IY+nn)FDCBnn8B
RES E,2,(IX+nn)DDCBnn93
RES E,2,(IY+nn)FDCBnn93
RES E,3,(IX+nn)DDCBnn9B
RES E,3,(IY+nn)FDCBnn9B
RES E,4,(IX+nn)DDCBnnA3
RES E,4,(IY+nn)FDCBnnA3
RES E,5,(IX+nn)DDCBnnAB
RES E,5,(IY+nn)FDCBnnAB
RES E,6,(IX+nn)DDCBnnB3
RES E,6,(IY+nn)FDCBnnB3
RES E,7,(IX+nn)DDCBnnBB
RES E,7,(IY+nn)FDCBnnBB
RES H,0,(IX+nn)DDCBnn84
RES H,0,(IY+nn)FDCBnn84
RES H,1,(IX+nn)DDCBnn8C
RES H,1,(IY+nn)FDCBnn8C
RES H,2,(IX+nn)DDCBnn94
RES H,2,(IY+nn)FDCBnn94
RES H,3,(IX+nn)DDCBnn9C
RES H,3,(IY+nn)FDCBnn9C
RES H,4,(IX+nn)DDCBnnA4
RES H,4,(IY+nn)FDCBnnA4
RES H,5,(IX+nn)DDCBnnAC
RES H,5,(IY+nn)FDCBnnAC
RES H,6,(IX+nn)DDCBnnB4
RES H,6,(IY+nn)FDCBnnB4
RES H,7,(IX+nn)DDCBnnBC
RES H,7,(IY+nn)FDCBnnBC
RES L,0,(IX+nn)DDCBnn85
RES L,0,(IY+nn)FDCBnn85
RES L,1,(IX+nn)DDCBnn8D
RES L,1,(IY+nn)FDCBnn8D
RES L,2,(IX+nn)DDCBnn95
RES L,2,(IY+nn)FDCBnn95
RES L,3,(IX+nn)DDCBnn9D
RES L,3,(IY+nn)FDCBnn9D
RES L,4,(IX+nn)DDCBnnA5
RES L,4,(IY+nn)FDCBnnA5
RES L,5,(IX+nn)DDCBnnAD
RES L,5,(IY+nn)FDCBnnAD
RES L,6,(IX+nn)DDCBnnB5
RES L,6,(IY+nn)FDCBnnB5
RES L,7,(IX+nn)DDCBnnBD
RES L,7,(IY+nn)FDCBnnBD
RET C9
RET CD8
RET NF8
RET NCD0
RET NZC0
RET PF0
RET PEE8
RET POE0
RET ZC8
RETIED4Dnn
RETNED45nn
RL (HL)CB16nn
RL (IX+d)DDCBnn16
RL (IY+d)FDCBnn16
RL ACB17nn
RL A,(IX+d)DDCBnn17
RL A,(IY+d)FDCBnn17
RL BCB10nn
RL B,(IX+d)DDCBnn10
RL B,(IY+d)FDCBnn10
RL CCB11nn
RL C,(IX+d)DDCBnn11
RL C,(IY+d)FDCBnn11
RL DCB12nn
RL D,(IX+d)DDCBnn12
RL D,(IY+d)FDCBnn12
RL ECB13nn
RL E,(IX+d)DDCBnn13
RL E,(IY+d)FDCBnn13
RL HCB14nn
RL H,(IX+d)DDCBnn14
RL H,(IY+d)FDCBnn14
RL LCB15nn
RL L,(IX+d)DDCBnn15
RL L,(IY+d)FDCBnn15
RLA17
RLC (HL)CB06nn
RLC (IX+d)DDCBnn06
RLC (IY+d)FDCBnn06
RLC ACB07nn
RLC A,(IX+d)DDCBnn07
RLC A,(IY+d)FDCBnn07
RLC BCB00nn
RLC B,(IX+d)DDCBnn00
RLC B,(IY+d)FDCBnn00
RLC CCB01nn
RLC C,(IX+d)DDCBnn01
RLC C,(IY+d)FDCBnn01
RLC DCB02nn
RLC D,(IX+d)DDCBnn02
RLC D,(IY+d)FDCBnn02
RLC ECB03nn
RLC E,(IX+d)DDCBnn03
RLC E,(IY+d)FDCBnn03
RLC HCB04nn
RLC H,(IX+d)DDCBnn04
RLC H,(IY+d)FDCBnn04
RLC LCB05nn
RLC L,(IX+d)DDCBnn05
RLC L,(IY+d)FDCBnn05
RLCA07
RLD (HL)ED6Fnn
RR (HL)CB1Enn
RR (IX+d)DDCBnn1E
RR (IY+d)FDCBnn1E
RR ACB1Fnn
RR A,(IX+d)DDCBnn1F
RR A,(IY+d)FDCBnn1F
RR BCB18nn
RR B,(IX+d)DDCBnn18
RR B,(IY+d)FDCBnn18
RR CCB19nn
RR C,(IX+d)DDCBnn19
RR C,(IY+d)FDCBnn19
RR DCB1Ann
RR D,(IX+d)DDCBnn1A
RR D,(IY+d)FDCBnn1A
RR ECB1Bnn
RR E,(IX+d)DDCBnn1B
RR E,(IY+d)FDCBnn1B
RR HCB1Cnn
RR H,(IX+d)DDCBnn1C
RR H,(IY+d)FDCBnn1C
RR LCB1Dnn
RR L,(IX+d)DDCBnn1D
RR L,(IY+d)FDCBnn1D
RRA1F
RRC (HL)CB0Enn
RRC (IX+d)DDCBnn0E
RRC (IY+d)FDCBnn0E
RRC ACB0Fnn
RRC A,(IX+d)DDCBnn0F
RRC A,(IY+d)FDCBnn0F
RRC BCB08nn
RRC B,(IX+d)DDCBnn08
RRC B,(IY+d)FDCBnn08
RRC CCB09nn
RRC C,(IX+d)DDCBnn09
RRC C,(IY+d)FDCBnn09
RRC DCB0Ann
RRC D,(IX+d)DDCBnn0A
RRC D,(IY+d)FDCBnn0A
RRC ECB0Bnn
RRC E,(IX+d)DDCBnn0B
RRC E,(IY+d)FDCBnn0B
RRC HCB0Cnn
RRC H,(IX+d)DDCBnn0C
RRC H,(IY+d)FDCBnn0C
RRC LCB0Dnn
RRC L,(IX+d)DDCBnn0D
RRC L,(IY+d)FDCBnn0D
RRCA0F
RRD (HL)ED67nn
RST 0C7
RST 1CF
RST 2D7
RST 3DF
RST 4E7
RST 5EF
RST 6F7
RST 7FF
SBC A,(HL)9E
SBC A,(IX+d)DD9Enn
SBC A,(IY+d)FD9Enn
SBC A,A9F
SBC A,B98
SBC A,C99
SBC A,D9A
SBC A,E9B
SBC A,H9C
SBC A,IXhDD9C
SBC A,IXlDD9D
SBC A,IYhFD9C
SBC A,IYlFD9D
SBC A,L9D
SBC A,nDEnn
SBC HL,BCED42nn
SBC HL,DEED52nn
SBC HL,HLED62nn
SBC HL,SPED72nn
SCF37
SET 0,(HL)CBC6nn
SET 0,(IX+d)DDCBnnC6
SET 0,(IY+d)FDCBnnC6
SET 0,ACBC7nn
SET 0,BCBC0nn
SET 0,CCBC1nn
SET 0,DCBC2nn
SET 0,ECBC3nn
SET 0,HCBC4nn
SET 0,LCBC5nn
SET 1,(HL)CBCEnn
SET 1,(IX+d)DDCBnnCE
SET 1,(IY+d)FDCBnnCE
SET 1,ACBCFnn
SET 1,BCBC8nn
SET 1,CCBC9nn
SET 1,DCBCAnn
SET 1,ECBCBnn
SET 1,HCBCCnn
SET 1,LCBCDnn
SET 2,(HL)CBD6nn
SET 2,(IX+d)DDCBnnD6
SET 2,(IY+d)FDCBnnD6
SET 2,ACBD7nn
SET 2,BCBD0nn
SET 2,CCBD1nn
SET 2,DCBD2nn
SET 2,ECBD3nn
SET 2,HCBD4nn
SET 2,LCBD5nn
SET 3,(HL)CBDEnn
SET 3,(IX+d)DDCBnnDE
SET 3,(IY+d)FDCBnnDE
SET 3,ACBDFnn
SET 3,BCBD8nn
SET 3,CCBD9nn
SET 3,DCBDAnn
SET 3,ECBDBnn
SET 3,HCBDCnn
SET 3,LCBDDnn
SET 4,(HL)CBE6nn
SET 4,(IX+d)DDCBnnE6
SET 4,(IY+d)FDCBnnE6
SET 4,ACBE7nn
SET 4,BCBE0nn
SET 4,CCBE1nn
SET 4,DCBE2nn
SET 4,ECBE3nn
SET 4,HCBE4nn
SET 4,LCBE5nn
SET 5,(HL)CBEEnn
SET 5,(IX+d)DDCBnnEE
SET 5,(IY+d)FDCBnnEE
SET 5,ACBEFnn
SET 5,BCBE8nn
SET 5,CCBE9nn
SET 5,DCBEAnn
SET 5,ECBEBnn
SET 5,HCBECnn
SET 5,LCBEDnn
SET 6,(HL)CBF6nn
SET 6,(IX+d)DDCBnnF6
SET 6,(IY+d)FDCBnnF6
SET 6,ACBF7nn
SET 6,BCBF0nn
SET 6,CCBF1nn
SET 6,DCBF2nn
SET 6,ECBF3nn
SET 6,HCBF4nn
SET 6,LCBF5nn
SET 7,(HL)CBFEnn
SET 7,(IX+d)DDCBnnFE
SET 7,(IY+d)FDCBnnFE
SET 7,ACBFFnn
SET 7,BCBF8nn
SET 7,CCBF9nn
SET 7,DCBFAnn
SET 7,ECBFBnn
SET 7,HCBFCnn
SET 7,LCBFDnn
SET A,0,(IX+nn)DDCBnnC7
SET A,0,(IY+nn)FDCBnnC7
SET A,1,(IX+nn)DDCBnnCF
SET A,1,(IY+nn)FDCBnnCF
SET A,2,(IX+nn)DDCBnnD7
SET A,2,(IY+nn)FDCBnnD7
SET A,3,(IX+nn)DDCBnnDF
SET A,3,(IY+nn)FDCBnnDF
SET A,4,(IX+nn)DDCBnnE7
SET A,4,(IY+nn)FDCBnnE7
SET A,5,(IX+nn)DDCBnnEF
SET A,5,(IY+nn)FDCBnnEF
SET A,6,(IX+nn)DDCBnnF7
SET A,6,(IY+nn)FDCBnnF7
SET A,7,(IX+nn)DDCBnnFF
SET A,7,(IY+nn)FDCBnnFF
SET B,0,(IX+nn)DDCBnnC0
SET B,0,(IY+nn)FDCBnnC0
SET B,1,(IX+nn)DDCBnnC8
SET B,1,(IY+nn)FDCBnnC8
SET B,2,(IX+nn)DDCBnnD0
SET B,2,(IY+nn)FDCBnnD0
SET B,3,(IX+nn)DDCBnnD8
SET B,3,(IY+nn)FDCBnnD8
SET B,4,(IX+nn)DDCBnnE0
SET B,4,(IY+nn)FDCBnnE0
SET B,5,(IX+nn)DDCBnnE8
SET B,5,(IY+nn)FDCBnnE8
SET B,6,(IX+nn)DDCBnnF0
SET B,6,(IY+nn)FDCBnnF0
SET B,7,(IX+nn)DDCBnnF8
SET B,7,(IY+nn)FDCBnnF8
SET C,0,(IX+nn)DDCBnnC1
SET C,0,(IY+nn)FDCBnnC1
SET C,1,(IX+nn)DDCBnnC9
SET C,1,(IY+nn)FDCBnnC9
SET C,2,(IX+nn)DDCBnnD1
SET C,2,(IY+nn)FDCBnnD1
SET C,3,(IX+nn)DDCBnnD9
SET C,3,(IY+nn)FDCBnnD9
SET C,4,(IX+nn)DDCBnnE1
SET C,4,(IY+nn)FDCBnnE1
SET C,5,(IX+nn)DDCBnnE9
SET C,5,(IY+nn)FDCBnnE9
SET C,6,(IX+nn)DDCBnnF1
SET C,6,(IY+nn)FDCBnnF1
SET C,7,(IX+nn)DDCBnnF9
SET C,7,(IY+nn)FDCBnnF9
SET D,0,(IX+nn)DDCBnnC2
SET D,0,(IY+nn)FDCBnnC2
SET D,1,(IX+nn)DDCBnnCA
SET D,1,(IY+nn)FDCBnnCA
SET D,2,(IX+nn)DDCBnnD2
SET D,2,(IY+nn)FDCBnnD2
SET D,3,(IX+nn)DDCBnnDA
SET D,3,(IY+nn)FDCBnnDA
SET D,4,(IX+nn)DDCBnnE2
SET D,4,(IY+nn)FDCBnnE2
SET D,5,(IX+nn)DDCBnnEA
SET D,5,(IY+nn)FDCBnnEA
SET D,6,(IX+nn)DDCBnnF2
SET D,6,(IY+nn)FDCBnnF2
SET D,7,(IX+nn)DDCBnnFA
SET D,7,(IY+nn)FDCBnnFA
SET E,0,(IX+nn)DDCBnnC3
SET E,0,(IY+nn)FDCBnnC3
SET E,1,(IX+nn)DDCBnnCB
SET E,1,(IY+nn)FDCBnnCB
SET E,2,(IX+nn)DDCBnnD3
SET E,2,(IY+nn)FDCBnnD3
SET E,3,(IX+nn)DDCBnnDB
SET E,3,(IY+nn)FDCBnnDB
SET E,4,(IX+nn)DDCBnnE3
SET E,4,(IY+nn)FDCBnnE3
SET E,5,(IX+nn)DDCBnnEB
SET E,5,(IY+nn)FDCBnnEB
SET E,6,(IX+nn)DDCBnnF3
SET E,6,(IY+nn)FDCBnnF3
SET E,7,(IX+nn)DDCBnnFB
SET E,7,(IY+nn)FDCBnnFB
SET H,0,(IX+nn)DDCBnnC4
SET H,0,(IY+nn)FDCBnnC4
SET H,1,(IX+nn)DDCBnnCC
SET H,1,(IY+nn)FDCBnnCC
SET H,2,(IX+nn)DDCBnnD4
SET H,2,(IY+nn)FDCBnnD4
SET H,3,(IX+nn)DDCBnnDC
SET H,3,(IY+nn)FDCBnnDC
SET H,4,(IX+nn)DDCBnnE4
SET H,4,(IY+nn)FDCBnnE4
SET H,5,(IX+nn)DDCBnnEC
SET H,5,(IY+nn)FDCBnnEC
SET H,6,(IX+nn)DDCBnnF4
SET H,6,(IY+nn)FDCBnnF4
SET H,7,(IX+nn)DDCBnnFC
SET H,7,(IY+nn)FDCBnnFC
SET L,0,(IX+nn)DDCBnnC5
SET L,0,(IY+nn)FDCBnnC5
SET L,1,(IX+nn)DDCBnnCD
SET L,1,(IY+nn)FDCBnnCD
SET L,2,(IX+nn)DDCBnnD5
SET L,2,(IY+nn)FDCBnnD5
SET L,3,(IX+nn)DDCBnnDD
SET L,3,(IY+nn)FDCBnnDD
SET L,4,(IX+nn)DDCBnnE5
SET L,4,(IY+nn)FDCBnnE5
SET L,5,(IX+nn)DDCBnnED
SET L,5,(IY+nn)FDCBnnED
SET L,6,(IX+nn)DDCBnnF5
SET L,6,(IY+nn)FDCBnnF5
SET L,7,(IX+nn)DDCBnnFD
SET L,7,(IY+nn)FDCBnnFD
SLA (HL)CB26nn
SLA (IX+d)DDCBnn26
SLA (IY+d)FDCBnn26
SLA ACB27nn
SLA A,(IX+d)DDCBnn27
SLA A,(IY+d)FDCBnn27
SLA BCB20nn
SLA B,(IX+d)DDCBnn20
SLA B,(IY+d)FDCBnn20
SLA CCB21nn
SLA C,(IX+d)DDCBnn21
SLA C,(IY+d)FDCBnn21
SLA DCB22nn
SLA D,(IX+d)DDCBnn22
SLA D,(IY+d)FDCBnn22
SLA ECB23nn
SLA E,(IX+d)DDCBnn23
SLA E,(IY+d)FDCBnn23
SLA HCB24nn
SLA H,(IX+d)DDCBnn24
SLA H,(IY+d)FDCBnn24
SLA LCB25nn
SLA L,(IX+d)DDCBnn25
SLA L,(IY+d)FDCBnn25
SLL (HL)CB36
SLL (IX+dd)DDCBnn36
SLL (IY+dd)FDCBnn36
SLL ACB37
SLL A,(IX+d)DDCBnn37
SLL A,(IY+d)FDCBnn37
SLL BCB30
SLL B,(IX+d)DDCBnn30
SLL B,(IY+d)FDCBnn30
SLL CCB31
SLL C,(IX+d)DDCBnn31
SLL C,(IY+d)FDCBnn31
SLL DCB32
SLL D,(IX+d)DDCBnn32
SLL D,(IY+d)FDCBnn32
SLL ECB33
SLL E,(IX+d)DDCBnn33
SLL E,(IY+d)FDCBnn33
SLL HCB34
SLL H,(IX+d)DDCBnn34
SLL H,(IY+d)FDCBnn34
SLL LCB35
SLL L,(IX+d)DDCBnn35
SLL L,(IY+d)FDCBnn35
SRA (HL)CB2Enn
SRA (IX+d)DDCBnn2E
SRA (IY+d)FDCBnn2E
SRA ACB2Fnn
SRA A,(IX+d)DDCBnn2F
SRA A,(IY+d)FDCBnn2F
SRA BCB28nn
SRA B,(IX+d)DDCBnn28
SRA B,(IY+d)FDCBnn28
SRA CCB29nn
SRA C,(IX+d)DDCBnn29
SRA C,(IY+d)FDCBnn29
SRA DCB2Ann
SRA D,(IX+d)DDCBnn2A
SRA D,(IY+d)FDCBnn2A
SRA ECB2Bnn
SRA E,(IX+d)DDCBnn2B
SRA E,(IY+d)FDCBnn2B
SRA HCB2Cnn
SRA H,(IX+d)DDCBnn2C
SRA H,(IY+d)FDCBnn2C
SRA LCB2Dnn
SRA L,(IX+d)DDCBnn2D
SRA L,(IY+d)FDCBnn2D
SRL (HL)CB3Enn
SRL (IX+d)DDCBnn3E
SRL (IY+d)FDCBnn3E
SRL ACB3Fnn
SRL A,(IX+d)DDCBnn3F
SRL A,(IY+d)FDCBnn3F
SRL BCB38nn
SRL B,(IX+d)DDCBnn38
SRL B,(IY+d)FDCBnn38
SRL CCB39nn
SRL C,(IX+d)DDCBnn39
SRL C,(IY+d)FDCBnn39
SRL DCB3Ann
SRL D,(IX+d)DDCBnn3A
SRL D,(IY+d)FDCBnn3A
SRL ECB3Bnn
SRL E,(IX+d)DDCBnn3B
SRL E,(IY+d)FDCBnn3B
SRL HCB3Cnn
SRL H,(IX+d)DDCBnn3C
SRL H,(IY+d)FDCBnn3C
SRL LCB3Dnn
SRL L,(IX+d)DDCBnn3D
SRL L,(IY+d)FDCBnn3D
SUB A,(HL)96
SUB A,(IX+d)DD96nn
SUB A,(IY+d)FD96nn
SUB A,A97
SUB A,B90
SUB A,C91
SUB A,D92
SUB A,E93
SUB A,H94
SUB A,L95
SUB A,nD6nn
SUB IXhDD94
SUB IXlDD95
SUB IYhFD94
SUB IYlFD95
XOR A,(HL)AE
XOR A,(IX+d)DDAEnn
XOR A,(IY+d)FDAEnn
XOR A,AAF
XOR A,BA8
XOR A,CA9
XOR A,DAA
XOR A,EAB
XOR A,HAC
XOR A,LAD
XOR A,nEEnn
XOR IXhDDAC
XOR IXlDDAD
XOR IYhFDAC
XOR IYlFDAD

6.2 - Instruction List by opcode

NOP00
LD BC, nn01nnnn
LD (BC), A02
INC BC03
INC B04
DEC B05
LD B, n06nn
RLCA07
EX AF, AF'08
ADD HL,BC09
LD A, (BC)0A
DEC BC0B
INC C0C
DEC C0D
LD C, n0Enn
RRCA0F
DJNZ e10nn
LD DE, nn11nnnn
LD (DE), A12
INC DE13
INC D14
DEC D15
LD D, n16nn
RLA17
JR e18nn
ADD HL,DE19
LD A, (DE)1A
DEC DE1B
INC E1C
DEC E1D
LD E, n1Enn
RRA1F
JR NZ,e20nn
LD HL, nn21nnnn
LD (nn), HL22nnnn
INC HL23
INC H24
DEC H25
LD H, n26nn
DAA27
JR Z,e28nn
ADD HL,HL29
LD HL, (nn)2Annnn
DEC HL2B
INC L2C
DEC L2D
LD L, n2Enn
CPL2F
CPL2F
JR NC,e30nn
LD SP, nn31nnnn
LD (nn), A32nnnn
INC SP33
INC (HL)34
DEC (HL)35
LD (HL), n36nn
SCF37
JR C,e38nn
ADD HL,SP39
LD A, (nn)3Annnn
DEC SP3B
INC A3C
DEC A3D
LD A, n3Enn
CCF3F
CCF3F
LD B, B40
LD B, C41
LD B, D42
LD B, E43
LD B, H44
LD B, L45
LD B, (HL)46
LD B, A47
LD C, B48
LD C, C49
LD C, D4A
LD C, E4B
LD C, H4C
LD C, L4D
LD C, (HL)4E
LD C, A4F
LD D, B50
LD D, C51
LD D, D52
LD D, E53
LD D, H54
LD D, L55
LD D, (HL)56
LD D, A57
LD E, B58
LD E, C59
LD E, D5A
LD E, E5B
LD E, H5C
LD E, L5D
LD E, (HL)5E
LD E, A5F
LD H, B60
LD H, C61
LD H, D62
LD H, E63
LD H, H64
LD H, L65
LD H, (HL)66
LD H, A67
LD L, B68
LD L, C69
LD L, D6A
LD L, E6B
LD L, H6C
LD L, L6D
LD L, (HL)6E
LD L, A6F
LD (HL), B70
LD (HL), C71
LD (HL), D72
LD (HL), E73
LD (HL), H74
LD (HL), L75
HALT76
LD (HL), A77
LD A, B78
LD A, C79
LD A, D7A
LD A, E7B
LD A, H7C
LD A, L7D
LD A, (HL)7E
LD A, A7F
ADD A,B80
ADD A,C81
ADD A,D82
ADD A,E83
ADD A,H84
ADD A,L85
ADD A,(HL)86
ADD A,A87
ADC A,B88
ADC A,C89
ADC A,D8A
ADC A,E8B
ADC A,H8C
ADC A,L8D
ADC A,(HL)8E
ADC A,A8F
SUB A,B90
SUB A,C91
SUB A,D92
SUB A,E93
SUB A,H94
SUB A,L95
SUB A,(HL)96
SUB A,A97
SBC A,B98
SBC A,C99
SBC A,D9A
SBC A,E9B
SBC A,H9C
SBC A,L9D
SBC A,(HL)9E
SBC A,A9F
AND A,BA0
AND A,CA1
AND A,DA2
AND A,EA3
AND A,HA4
AND A,LA5
AND A,(HL)A6
AND A,AA7
XOR A,BA8
XOR A,CA9
XOR A,DAA
XOR A,EAB
XOR A,HAC
XOR A,LAD
XOR A,(HL)AE
XOR A,AAF
OR A,BB0
OR A,CB1
OR A,DB2
OR A,EB3
OR A,HB4
OR A,LB5
OR A,(HL)B6
OR A,AB7
CP BB8
CP CB9
CP DBA
CP EBB
CP HBC
CP LBD
CP (HL)BE
CP ABF
RET NZC0
POP BCC1
JP NZ,nnC2nnnn
JP nnC3nnnn
CALL NZ,nnC4nnnn
PUSH BCC5
ADD A,nC6nn
RST 0C7
RET ZC8
RET C9
JP Z,nnCAnnnn
RLC BCB00nn
RLC CCB01nn
RLC DCB02nn
RLC ECB03nn
RLC HCB04nn
RLC LCB05nn
RLC (HL)CB06nn
RLC ACB07nn
RRC BCB08nn
RRC CCB09nn
RRC DCB0Ann
RRC ECB0Bnn
RRC HCB0Cnn
RRC LCB0Dnn
RRC (HL)CB0Enn
RRC ACB0Fnn
RL BCB10nn
RL CCB11nn
RL DCB12nn
RL ECB13nn
RL HCB14nn
RL LCB15nn
RL (HL)CB16nn
RL ACB17nn
RR BCB18nn
RR CCB19nn
RR DCB1Ann
RR ECB1Bnn
RR HCB1Cnn
RR LCB1Dnn
RR (HL)CB1Enn
RR ACB1Fnn
SLA BCB20nn
SLA CCB21nn
SLA DCB22nn
SLA ECB23nn
SLA HCB24nn
SLA LCB25nn
SLA (HL)CB26nn
SLA ACB27nn
SRA BCB28nn
SRA CCB29nn
SRA DCB2Ann
SRA ECB2Bnn
SRA HCB2Cnn
SRA LCB2Dnn
SRA (HL)CB2Enn
SRA ACB2Fnn
SLL BCB30
SLL CCB31
SLL DCB32
SLL ECB33
SLL HCB34
SLL LCB35
SLL (HL)CB36
SLL ACB37
SRL BCB38nn
SRL CCB39nn
SRL DCB3Ann
SRL ECB3Bnn
SRL HCB3Cnn
SRL LCB3Dnn
SRL (HL)CB3Enn
SRL ACB3Fnn
BIT 0,BCB40nn
BIT 0,CCB41nn
BIT 0,DCB42nn
BIT 0,ECB43nn
BIT 0,HCB44nn
BIT 0,LCB45nn
BIT 0,(HL)CB46nn
BIT 0,ACB47nn
BIT 1,BCB48nn
BIT 1,CCB49nn
BIT 1,DCB4Ann
BIT 1,ECB4Bnn
BIT 1,HCB4Cnn
BIT 1,LCB4Dnn
BIT 1,(HL)CB4Enn
BIT 1,ACB4Fnn
BIT 2,BCB50nn
BIT 2,CCB51nn
BIT 2,DCB52nn
BIT 2,ECB53nn
BIT 2,HCB54nn
BIT 2,LCB55nn
BIT 2,(HL)CB56nn
BIT 2,ACB57nn
BIT 3,BCB58nn
BIT 3,CCB59nn
BIT 3,DCB5Ann
BIT 3,ECB5Bnn
BIT 3,HCB5Cnn
BIT 3,LCB5Dnn
BIT 3,(HL)CB5Enn
BIT 3,ACB5Fnn
BIT 4,BCB60nn
BIT 4,CCB61nn
BIT 4,DCB62nn
BIT 4,ECB63nn
BIT 4,HCB64nn
BIT 4,LCB65nn
BIT 4,(HL)CB66nn
BIT 4,ACB67nn
BIT 5,BCB68nn
BIT 5,CCB69nn
BIT 5,DCB6Ann
BIT 5,ECB6Bnn
BIT 5,HCB6Cnn
BIT 5,LCB6Dnn
BIT 5,(HL)CB6Enn
BIT 5,ACB6Fnn
BIT 6,BCB70nn
BIT 6,CCB71nn
BIT 6,DCB72nn
BIT 6,ECB73nn
BIT 6,HCB74nn
BIT 6,LCB75nn
BIT 6,(HL)CB76nn
BIT 6,ACB77nn
BIT 7,BCB78nn
BIT 7,CCB79nn
BIT 7,DCB7Ann
BIT 7,ECB7Bnn
BIT 7,HCB7Cnn
BIT 7,LCB7Dnn
BIT 7,(HL)CB7Enn
BIT 7,ACB7Fnn
RES 0,BCB80nn
RES 0,CCB81nn
RES 0,DCB82nn
RES 0,ECB83nn
RES 0,HCB84nn
RES 0,LCB85nn
RES 0,(HL)CB86nn
RES 0,ACB87nn
RES 1,BCB88nn
RES 1,CCB89nn
RES 1,DCB8Ann
RES 1,ECB8Bnn
RES 1,HCB8Cnn
RES 1,LCB8Dnn
RES 1,(HL)CB8Enn
RES 1,ACB8Fnn
RES 2,BCB90nn
RES 2,CCB91nn
RES 2,DCB92nn
RES 2,ECB93nn
RES 2,HCB94nn
RES 2,LCB95nn
RES 2,(HL)CB96nn
RES 2,ACB97nn
RES 3,BCB98nn
RES 3,CCB99nn
RES 3,DCB9Ann
RES 3,ECB9Bnn
RES 3,HCB9Cnn
RES 3,LCB9Dnn
RES 3,(HL)CB9Enn
RES 3,ACB9Fnn
RES 4,BCBA0nn
RES 4,CCBA1nn
RES 4,DCBA2nn
RES 4,ECBA3nn
RES 4,HCBA4nn
RES 4,LCBA5nn
RES 4,(HL)CBA6nn
RES 4,ACBA7nn
RES 5,BCBA8nn
RES 5,CCBA9nn
RES 5,DCBAAnn
RES 5,ECBABnn
RES 5,HCBACnn
RES 5,LCBADnn
RES 5,(HL)CBAEnn
RES 5,ACBAFnn
RES 6,BCBB0nn
RES 6,CCBB1nn
RES 6,DCBB2nn
RES 6,ECBB3nn
RES 6,HCBB4nn
RES 6,LCBB5nn
RES 6,(HL)CBB6nn
RES 6,ACBB7nn
RES 7,BCBB8nn
RES 7,CCBB9nn
RES 7,DCBBAnn
RES 7,ECBBBnn
RES 7,HCBBCnn
RES 7,LCBBDnn
RES 7,(HL)CBBEnn
RES 7,ACBBFnn
SET 0,BCBC0nn
SET 0,CCBC1nn
SET 0,DCBC2nn
SET 0,ECBC3nn
SET 0,HCBC4nn
SET 0,LCBC5nn
SET 0,(HL)CBC6nn
SET 0,ACBC7nn
SET 1,BCBC8nn
SET 1,CCBC9nn
SET 1,DCBCAnn
SET 1,ECBCBnn
SET 1,HCBCCnn
SET 1,LCBCDnn
SET 1,(HL)CBCEnn
SET 1,ACBCFnn
SET 2,BCBD0nn
SET 2,CCBD1nn
SET 2,DCBD2nn
SET 2,ECBD3nn
SET 2,HCBD4nn
SET 2,LCBD5nn
SET 2,(HL)CBD6nn
SET 2,ACBD7nn
SET 3,BCBD8nn
SET 3,CCBD9nn
SET 3,DCBDAnn
SET 3,ECBDBnn
SET 3,HCBDCnn
SET 3,LCBDDnn
SET 3,(HL)CBDEnn
SET 3,ACBDFnn
SET 4,BCBE0nn
SET 4,CCBE1nn
SET 4,DCBE2nn
SET 4,ECBE3nn
SET 4,HCBE4nn
SET 4,LCBE5nn
SET 4,(HL)CBE6nn
SET 4,ACBE7nn
SET 5,BCBE8nn
SET 5,CCBE9nn
SET 5,DCBEAnn
SET 5,ECBEBnn
SET 5,HCBECnn
SET 5,LCBEDnn
SET 5,(HL)CBEEnn
SET 5,ACBEFnn
SET 6,BCBF0nn
SET 6,CCBF1nn
SET 6,DCBF2nn
SET 6,ECBF3nn
SET 6,HCBF4nn
SET 6,LCBF5nn
SET 6,(HL)CBF6nn
SET 6,ACBF7nn
SET 7,BCBF8nn
SET 7,CCBF9nn
SET 7,DCBFAnn
SET 7,ECBFBnn
SET 7,HCBFCnn
SET 7,LCBFDnn
SET 7,(HL)CBFEnn
SET 7,ACBFFnn
CALL Z,nnCCnnnn
CALL nnCDnnnn
ADC A,nCEnn
RST 1CF
RET NCD0
POP DED1
JP NC,nnD2nnnn
OUT (n),AD3nn
CALL NC,nnD4nnnn
PUSH DED5
SUB A,nD6nn
RST 2D7
RET CD8
EXXD9
JP C,nnDAnnnn
IN A,(n)DBnn
CALL C,nnDCnnnn
ADD IX,BCDD09nn
ADD IX,DEDD19nn
LD IX, nnDD21nnnn
LD (nn), IXDD22nnnn
INC IXDD23nn
INC IXhDD24
DEC IXhDD25
LD IXh,nDD26nn
ADD IX,IXDD29nn
LD IX, (nn)DD2Annnn
DEC IXDD2Bnn
INC IXlDD2C
DEC IXlDD2D
LD IXl,nDD2Enn
INC (IX+d)DD34nn
DEC (IX+d)DD35nn
LD (IX+d), nDD36nnnn
ADD IX,SPDD39nn
LD B,IXhDD44
LD B,IXlDD45
LD B, (IX+d)DD46nn
LD C,IXhDD4C
LD C,IXlDD4D
LD C, (IX+d)DD4Enn
LD D,IXhDD54
LD D,IXlDD55
LD D, (IX+d)DD56nn
LD E,IXhDD5C
LD E,IXlDD5D
LD E, (IX+d)DD5Enn
LD IXh,BDD60
LD IXh,CDD61
LD IXh,DDD62
LD IXh,EDD63
LD IXh,IHhDD64
LD IXh,IHlDD65
LD H, (IX+d)DD66nn
LD IXh,ADD67
LD IXl,BDD68
LD IXl,CDD69
LD IXl,DDD6A
LD IXl,EDD6B
LD IXl,IHhDD6C
LD IXl,IHlDD6D
LD L, (IX+d)DD6Enn
LD IXl,ADD6F
LD (IX+d), BDD70nn
LD (IX+d), CDD71nn
LD (IX+d), DDD72nn
LD (IX+d), EDD73nn
LD (IX+d), HDD74nn
LD (IX+d), LDD75nn
LD (IX+d), ADD77nn
LD A,IXhDD7C
LD A,IXlDD7D
LD A, (IX+d)DD7Enn
ADD A,IXhDD84
ADD A,IXlDD85
ADD A,(IX+d)DD86nn
ADC A,IXhDD8C
ADC A,IXlDD8D
ADC A,(IX+d)DD8Enn
SUB IXhDD94
SUB IXlDD95
SUB A,(IX+d)DD96nn
SBC A,IXhDD9C
SBC A,IXlDD9D
SBC A,(IX+d)DD9Enn
AND IXhDDA4
AND IXlDDA5
AND A,(IX+d)DDA6nn
XOR IXhDDAC
XOR IXlDDAD
XOR A,(IX+d)DDAEnn
OR IXhDDB4
OR IXlDDB5
OR A,(IX+d)DDB6nn
CP IXhDDBC
CP IXlDDBD
CP (IX+d)DDBEnn
RLC B,(IX+d)DDCBnn00
RLC C,(IX+d)DDCBnn01
RLC D,(IX+d)DDCBnn02
RLC E,(IX+d)DDCBnn03
RLC H,(IX+d)DDCBnn04
RLC L,(IX+d)DDCBnn05
RLC (IX+d)DDCBnn06
RLC A,(IX+d)DDCBnn07
RRC B,(IX+d)DDCBnn08
RRC C,(IX+d)DDCBnn09
RRC D,(IX+d)DDCBnn0A
RRC E,(IX+d)DDCBnn0B
RRC H,(IX+d)DDCBnn0C
RRC L,(IX+d)DDCBnn0D
RRC (IX+d)DDCBnn0E
RRC A,(IX+d)DDCBnn0F
RL B,(IX+d)DDCBnn10
RL C,(IX+d)DDCBnn11
RL D,(IX+d)DDCBnn12
RL E,(IX+d)DDCBnn13
RL H,(IX+d)DDCBnn14
RL L,(IX+d)DDCBnn15
RL (IX+d)DDCBnn16
RL A,(IX+d)DDCBnn17
RR B,(IX+d)DDCBnn18
RR C,(IX+d)DDCBnn19
RR D,(IX+d)DDCBnn1A
RR E,(IX+d)DDCBnn1B
RR H,(IX+d)DDCBnn1C
RR L,(IX+d)DDCBnn1D
RR (IX+d)DDCBnn1E
RR A,(IX+d)DDCBnn1F
SLA B,(IX+d)DDCBnn20
SLA C,(IX+d)DDCBnn21
SLA D,(IX+d)DDCBnn22
SLA E,(IX+d)DDCBnn23
SLA H,(IX+d)DDCBnn24
SLA L,(IX+d)DDCBnn25
SLA (IX+d)DDCBnn26
SLA A,(IX+d)DDCBnn27
SRA B,(IX+d)DDCBnn28
SRA C,(IX+d)DDCBnn29
SRA D,(IX+d)DDCBnn2A
SRA E,(IX+d)DDCBnn2B
SRA H,(IX+d)DDCBnn2C
SRA L,(IX+d)DDCBnn2D
SRA (IX+d)DDCBnn2E
SRA A,(IX+d)DDCBnn2F
SLL B,(IX+d)DDCBnn30
SLL C,(IX+d)DDCBnn31
SLL D,(IX+d)DDCBnn32
SLL E,(IX+d)DDCBnn33
SLL H,(IX+d)DDCBnn34
SLL L,(IX+d)DDCBnn35
SLL (IX+dd)DDCBnn36
SLL A,(IX+d)DDCBnn37
SRL B,(IX+d)DDCBnn38
SRL C,(IX+d)DDCBnn39
SRL D,(IX+d)DDCBnn3A
SRL E,(IX+d)DDCBnn3B
SRL H,(IX+d)DDCBnn3C
SRL L,(IX+d)DDCBnn3D
SRL (IX+d)DDCBnn3E
SRL A,(IX+d)DDCBnn3F
BIT 0,(IX+d)DDCBnn40
BIT 0,(IX+d)DDCBnn41
BIT 0,(IX+d)DDCBnn42
BIT 0,(IX+d)DDCBnn43
BIT 0,(IX+d)DDCBnn44
BIT 0,(IX+d)DDCBnn45
BIT 0,(IX+d)DDCBnn46
BIT 0,(IX+d)DDCBnn47
BIT 1,(IX+d)DDCBnn48
BIT 1,(IX+d)DDCBnn49
BIT 1,(IX+d)DDCBnn4A
BIT 1,(IX+d)DDCBnn4B
BIT 1,(IX+d)DDCBnn4C
BIT 1,(IX+d)DDCBnn4D
BIT 1,(IX+d)DDCBnn4E
BIT 1,(IX+d)DDCBnn4F
BIT 2,(IX+d)DDCBnn50
BIT 2,(IX+d)DDCBnn51
BIT 2,(IX+d)DDCBnn52
BIT 2,(IX+d)DDCBnn53
BIT 2,(IX+d)DDCBnn54
BIT 2,(IX+d)DDCBnn55
BIT 2,(IX+d)DDCBnn56
BIT 2,(IX+d)DDCBnn57
BIT 3,(IX+d)DDCBnn58
BIT 3,(IX+d)DDCBnn59
BIT 3,(IX+d)DDCBnn5A
BIT 3,(IX+d)DDCBnn5B
BIT 3,(IX+d)DDCBnn5C
BIT 3,(IX+d)DDCBnn5D
BIT 3,(IX+d)DDCBnn5E
BIT 3,(IX+d)DDCBnn5F
BIT 4,(IX+d)DDCBnn60
BIT 4,(IX+d)DDCBnn61
BIT 4,(IX+d)DDCBnn62
BIT 4,(IX+d)DDCBnn63
BIT 4,(IX+d)DDCBnn64
BIT 4,(IX+d)DDCBnn65
BIT 4,(IX+d)DDCBnn66
BIT 4,(IX+d)DDCBnn67
BIT 5,(IX+d)DDCBnn68
BIT 5,(IX+d)DDCBnn69
BIT 5,(IX+d)DDCBnn6A
BIT 5,(IX+d)DDCBnn6B
BIT 5,(IX+d)DDCBnn6C
BIT 5,(IX+d)DDCBnn6D
BIT 5,(IX+d)DDCBnn6E
BIT 5,(IX+d)DDCBnn6F
BIT 6,(IX+d)DDCBnn70
BIT 6,(IX+d)DDCBnn71
BIT 6,(IX+d)DDCBnn72
BIT 6,(IX+d)DDCBnn73
BIT 6,(IX+d)DDCBnn74
BIT 6,(IX+d)DDCBnn75
BIT 6,(IX+d)DDCBnn76
BIT 6,(IX+d)DDCBnn77
BIT 7,(IX+d)DDCBnn78
BIT 7,(IX+d)DDCBnn79
BIT 7,(IX+d)DDCBnn7A
BIT 7,(IX+d)DDCBnn7B
BIT 7,(IX+d)DDCBnn7C
BIT 7,(IX+d)DDCBnn7D
BIT 7,(IX+d)DDCBnn7E
BIT 7,(IX+d)DDCBnn7F
RES B,0,(IX+nn)DDCBnn80
RES C,0,(IX+nn)DDCBnn81
RES D,0,(IX+nn)DDCBnn82
RES E,0,(IX+nn)DDCBnn83
RES H,0,(IX+nn)DDCBnn84
RES L,0,(IX+nn)DDCBnn85
RES 0,(IX+d)DDCBnn86
RES A,0,(IX+nn)DDCBnn87
RES B,1,(IX+nn)DDCBnn88
RES C,1,(IX+nn)DDCBnn89
RES D,1,(IX+nn)DDCBnn8A
RES E,1,(IX+nn)DDCBnn8B
RES H,1,(IX+nn)DDCBnn8C
RES L,1,(IX+nn)DDCBnn8D
RES 1,(IX+d)DDCBnn8E
RES A,1,(IX+nn)DDCBnn8F
RES B,2,(IX+nn)DDCBnn90
RES C,2,(IX+nn)DDCBnn91
RES D,2,(IX+nn)DDCBnn92
RES E,2,(IX+nn)DDCBnn93
RES H,2,(IX+nn)DDCBnn94
RES L,2,(IX+nn)DDCBnn95
RES 2,(IX+d)DDCBnn96
RES A,2,(IX+nn)DDCBnn97
RES B,3,(IX+nn)DDCBnn98
RES C,3,(IX+nn)DDCBnn99
RES D,3,(IX+nn)DDCBnn9A
RES E,3,(IX+nn)DDCBnn9B
RES H,3,(IX+nn)DDCBnn9C
RES L,3,(IX+nn)DDCBnn9D
RES 3,(IX+d)DDCBnn9E
RES A,3,(IX+nn)DDCBnn9F
RES B,4,(IX+nn)DDCBnnA0
RES C,4,(IX+nn)DDCBnnA1
RES D,4,(IX+nn)DDCBnnA2
RES E,4,(IX+nn)DDCBnnA3
RES H,4,(IX+nn)DDCBnnA4
RES L,4,(IX+nn)DDCBnnA5
RES 4,(IX+d)DDCBnnA6
RES A,4,(IX+nn)DDCBnnA7
RES B,5,(IX+nn)DDCBnnA8
RES C,5,(IX+nn)DDCBnnA9
RES D,5,(IX+nn)DDCBnnAA
RES E,5,(IX+nn)DDCBnnAB
RES H,5,(IX+nn)DDCBnnAC
RES L,5,(IX+nn)DDCBnnAD
RES 5,(IX+d)DDCBnnAE
RES A,5,(IX+nn)DDCBnnAF
RES B,6,(IX+nn)DDCBnnB0
RES C,6,(IX+nn)DDCBnnB1
RES D,6,(IX+nn)DDCBnnB2
RES E,6,(IX+nn)DDCBnnB3
RES H,6,(IX+nn)DDCBnnB4
RES L,6,(IX+nn)DDCBnnB5
RES 6,(IX+d)DDCBnnB6
RES A,6,(IX+nn)DDCBnnB7
RES B,7,(IX+nn)DDCBnnB8
RES C,7,(IX+nn)DDCBnnB9
RES D,7,(IX+nn)DDCBnnBA
RES E,7,(IX+nn)DDCBnnBB
RES H,7,(IX+nn)DDCBnnBC
RES L,7,(IX+nn)DDCBnnBD
RES 7,(IX+d)DDCBnnBE
RES A,7,(IX+nn)DDCBnnBF
SET B,0,(IX+nn)DDCBnnC0
SET C,0,(IX+nn)DDCBnnC1
SET D,0,(IX+nn)DDCBnnC2
SET E,0,(IX+nn)DDCBnnC3
SET H,0,(IX+nn)DDCBnnC4
SET L,0,(IX+nn)DDCBnnC5
SET 0,(IX+d)DDCBnnC6
SET A,0,(IX+nn)DDCBnnC7
SET B,1,(IX+nn)DDCBnnC8
SET C,1,(IX+nn)DDCBnnC9
SET D,1,(IX+nn)DDCBnnCA
SET E,1,(IX+nn)DDCBnnCB
SET H,1,(IX+nn)DDCBnnCC
SET L,1,(IX+nn)DDCBnnCD
SET 1,(IX+d)DDCBnnCE
SET A,1,(IX+nn)DDCBnnCF
SET B,2,(IX+nn)DDCBnnD0
SET C,2,(IX+nn)DDCBnnD1
SET D,2,(IX+nn)DDCBnnD2
SET E,2,(IX+nn)DDCBnnD3
SET H,2,(IX+nn)DDCBnnD4
SET L,2,(IX+nn)DDCBnnD5
SET 2,(IX+d)DDCBnnD6
SET A,2,(IX+nn)DDCBnnD7
SET B,3,(IX+nn)DDCBnnD8
SET C,3,(IX+nn)DDCBnnD9
SET D,3,(IX+nn)DDCBnnDA
SET E,3,(IX+nn)DDCBnnDB
SET H,3,(IX+nn)DDCBnnDC
SET L,3,(IX+nn)DDCBnnDD
SET 3,(IX+d)DDCBnnDE
SET A,3,(IX+nn)DDCBnnDF
SET B,4,(IX+nn)DDCBnnE0
SET C,4,(IX+nn)DDCBnnE1
SET D,4,(IX+nn)DDCBnnE2
SET E,4,(IX+nn)DDCBnnE3
SET H,4,(IX+nn)DDCBnnE4
SET L,4,(IX+nn)DDCBnnE5
SET 4,(IX+d)DDCBnnE6
SET A,4,(IX+nn)DDCBnnE7
SET B,5,(IX+nn)DDCBnnE8
SET C,5,(IX+nn)DDCBnnE9
SET D,5,(IX+nn)DDCBnnEA
SET E,5,(IX+nn)DDCBnnEB
SET H,5,(IX+nn)DDCBnnEC
SET L,5,(IX+nn)DDCBnnED
SET 5,(IX+d)DDCBnnEE
SET A,5,(IX+nn)DDCBnnEF
SET B,6,(IX+nn)DDCBnnF0
SET C,6,(IX+nn)DDCBnnF1
SET D,6,(IX+nn)DDCBnnF2
SET E,6,(IX+nn)DDCBnnF3
SET H,6,(IX+nn)DDCBnnF4
SET L,6,(IX+nn)DDCBnnF5
SET 6,(IX+d)DDCBnnF6
SET A,6,(IX+nn)DDCBnnF7
SET B,7,(IX+nn)DDCBnnF8
SET C,7,(IX+nn)DDCBnnF9
SET D,7,(IX+nn)DDCBnnFA
SET E,7,(IX+nn)DDCBnnFB
SET H,7,(IX+nn)DDCBnnFC
SET L,7,(IX+nn)DDCBnnFD
SET 7,(IX+d)DDCBnnFE
SET A,7,(IX+nn)DDCBnnFF
POP IXDDE1nn
EX (SP), IXDDE3nn
PUSH IXDDE5nn
JP (IX)DDE9nn
LD SP, IXDDF9nn
SBC A,nDEnn
RST 3DF
RET POE0
POP HLE1
JP PO,nnE2nnnn
EX (SP), HLE3
CALL PO,nnE4nnnn
PUSH HLE5
AND A,nE6nn
RST 4E7
RET PEE8
JP (HL)E9
JP PE,nnEAnnnn
EX DE, HLEB
CALL PE,nnECnnnn
IN B,(C)ED40nn
OUT (C),BED41nn
SBC HL,BCED42nn
LD (nn), BCED43nnnn
NEGED44nn
NEGED44nn
RETNED45nn
IM0ED46nn
LD I, AED47nn
IN C,(C)ED48nn
OUT (C),CED49nn
ADC HL,BCED4Ann
LD BC, (nn)ED4Bnnnn
RETIED4Dnn
LD R, AED4Fnn
IN D,(C)ED50nn
OUT (C),DED51nn
SBC HL,DEED52nn
LD (nn), DEED53nnnn
IM1ED56nn
LD A, IED57nn
IN E,(C)ED58nn
OUT (C),EED59nn
ADC HL,DEED5Ann
LD DE, (nn)ED5Bnnnn
IM2ED5Enn
LD A, RED5Fnn
IN H,(C)ED60nn
OUT (C),HED61nn
SBC HL,HLED62nn
LD (nn), HLED63nnnn
RRD (HL)ED67nn
IN L,(C)ED68nn
OUT (C),LED69nn
ADC HL,HLED6Ann
LD HL, (nn)ED6Bnnnn
RLD (HL)ED6Fnn
IN F,(C)ED70nn
OUT (C),FED71nn
SBC HL,SPED72nn
LD (nn), SPED73nnnn
OUT (C),AED79nn
ADC HL,SPED7Ann
IN A,(C)ED7Bnn
LD SP, (nn)ED7Bnnnn
LDIEDA0nn
CPIEDA1nn
INIEDA2nn
OUTIEDA3nn
LDDEDA8nn
CPDEDA9nn
INDEDAAnn
OUTDEDABnn
LDIREDB0nn
CPIREDB1nn
INIREDB2nn
OUTIREDB3nn
LDDREDB8nn
CPDREDB9nn
INDREDBAnn
OUTDREDBBnn
XOR A,nEEnn
RST 5EF
RET PF0
POP AFF1
JP P,nnF2nnnn
DIF3
CALL P,nnF4nnnn
PUSH AFF5
OR A,nF6nn
RST 6F7
RET NF8
LD SP, HLF9
JP N,nnFAnnnn
EIFB
CALL N,nnFCnnnn
ADD IY,BCFD09nn
ADD IY,DEFD19nn
LD IY, nnFD21nnnn
LD (nn), IYFD22nnnn
INC IYFD23nn
INC IYhFD24
DEC IYhFD25
LD IYh,nFD26nn
ADD IY,IYFD29nn
LD IY, (nn)FD2Annnn
DEC IYFD2Bnn
INC IYlFD2C
DEC IYlFD2D
LD IYl,nFD2Enn
INC (IY+d)FD34nn
DEC (IY+d)FD35nn
LD (IY+d), nFD36nnnn
ADD IY,SPFD39nn
LD B,IYhFD44
LD B,IYlFD45
LD B, (IY+d)FD46nn
LD C,IYhFD4C
LD C,IYlFD4D
LD C, (IY+d)FD4Enn
LD D,IYhFD54
LD D,IYlFD55
LD D, (IY+d)FD56nn
LD E,IYhFD5C
LD E,IYlFD5D
LD E, (IY+d)FD5Enn
LD IYh,BFD60
LD IYh,CFD61
LD IYh,DFD62
LD IYh,EFD63
LD IYh,IHhFD64
LD IYh,IHlFD65
LD H, (IY+d)FD66nn
LD IYh,AFD67
LD IYl,BFD68
LD IYl,CFD69
LD IYl,DFD6A
LD IYl,EFD6B
LD IYl,IHhFD6C
LD IYl,IHlFD6D
LD L, (IY+d)FD6Enn
LD IYl,AFD6F
LD (IY+d), BFD70nn
LD (IY+d), CFD71nn
LD (IY+d), DFD72nn
LD (IY+d), EFD73nn
LD (IY+d), HFD74nn
LD (IY+d), LFD75nn
LD (IY+d), AFD77nn
LD A,IYhFD7C
LD A,IYlFD7D
LD A, (IY+d)FD7Enn
ADD A,IYhFD84
ADD A,IYlFD85
ADD A,(IY+d)FD86nn
ADC A,IYhFD8C
ADC A,IYlFD8D
ADC A,(IY+d)FD8Enn
SUB IYhFD94
SUB IYlFD95
SUB A,(IY+d)FD96nn
SBC A,IYhFD9C
SBC A,IYlFD9D
SBC A,(IY+d)FD9Enn
AND IYhFDA4
AND IYlFDA5
AND A,(IY+d)FDA6nn
XOR IYhFDAC
XOR IYlFDAD
XOR A,(IY+d)FDAEnn
OR IYhFDB4
OR IYlFDB5
OR A,(IY+d)FDB6nn
CP IYhFDBC
CP IYlFDBD
CP (IY+d)FDBEnn
RLC B,(IY+d)FDCBnn00
RLC C,(IY+d)FDCBnn01
RLC D,(IY+d)FDCBnn02
RLC E,(IY+d)FDCBnn03
RLC H,(IY+d)FDCBnn04
RLC L,(IY+d)FDCBnn05
RLC (IY+d)FDCBnn06
RLC A,(IY+d)FDCBnn07
RRC B,(IY+d)FDCBnn08
RRC C,(IY+d)FDCBnn09
RRC D,(IY+d)FDCBnn0A
RRC E,(IY+d)FDCBnn0B
RRC H,(IY+d)FDCBnn0C
RRC L,(IY+d)FDCBnn0D
RRC (IY+d)FDCBnn0E
RRC A,(IY+d)FDCBnn0F
RL B,(IY+d)FDCBnn10
RL C,(IY+d)FDCBnn11
RL D,(IY+d)FDCBnn12
RL E,(IY+d)FDCBnn13
RL H,(IY+d)FDCBnn14
RL L,(IY+d)FDCBnn15
RL (IY+d)FDCBnn16
RL A,(IY+d)FDCBnn17
RR B,(IY+d)FDCBnn18
RR C,(IY+d)FDCBnn19
RR D,(IY+d)FDCBnn1A
RR E,(IY+d)FDCBnn1B
RR H,(IY+d)FDCBnn1C
RR L,(IY+d)FDCBnn1D
RR (IY+d)FDCBnn1E
RR A,(IY+d)FDCBnn1F
SLA B,(IY+d)FDCBnn20
SLA C,(IY+d)FDCBnn21
SLA D,(IY+d)FDCBnn22
SLA E,(IY+d)FDCBnn23
SLA H,(IY+d)FDCBnn24
SLA L,(IY+d)FDCBnn25
SLA (IY+d)FDCBnn26
SLA A,(IY+d)FDCBnn27
SRA B,(IY+d)FDCBnn28
SRA C,(IY+d)FDCBnn29
SRA D,(IY+d)FDCBnn2A
SRA E,(IY+d)FDCBnn2B
SRA H,(IY+d)FDCBnn2C
SRA L,(IY+d)FDCBnn2D
SRA (IY+d)FDCBnn2E
SRA A,(IY+d)FDCBnn2F
SLL B,(IY+d)FDCBnn30
SLL C,(IY+d)FDCBnn31
SLL D,(IY+d)FDCBnn32
SLL E,(IY+d)FDCBnn33
SLL H,(IY+d)FDCBnn34
SLL L,(IY+d)FDCBnn35
SLL (IY+dd)FDCBnn36
SLL A,(IY+d)FDCBnn37
SRL B,(IY+d)FDCBnn38
SRL C,(IY+d)FDCBnn39
SRL D,(IY+d)FDCBnn3A
SRL E,(IY+d)FDCBnn3B
SRL H,(IY+d)FDCBnn3C
SRL L,(IY+d)FDCBnn3D
SRL (IY+d)FDCBnn3E
SRL A,(IY+d)FDCBnn3F
BIT 0,(IY+d)FDCBnn40
BIT 0,(IY+d)FDCBnn41
BIT 0,(IY+d)FDCBnn42
BIT 0,(IY+d)FDCBnn43
BIT 0,(IY+d)FDCBnn44
BIT 0,(IY+d)FDCBnn45
BIT 0,(IY+d)FDCBnn46
BIT 0,(IY+d)FDCBnn47
BIT 1,(IY+d)FDCBnn48
BIT 1,(IY+d)FDCBnn49
BIT 1,(IY+d)FDCBnn4A
BIT 1,(IY+d)FDCBnn4B
BIT 1,(IY+d)FDCBnn4C
BIT 1,(IY+d)FDCBnn4D
BIT 1,(IY+d)FDCBnn4E
BIT 1,(IY+d)FDCBnn4F
BIT 2,(IY+d)FDCBnn50
BIT 2,(IY+d)FDCBnn51
BIT 2,(IY+d)FDCBnn52
BIT 2,(IY+d)FDCBnn53
BIT 2,(IY+d)FDCBnn54
BIT 2,(IY+d)FDCBnn55
BIT 2,(IY+d)FDCBnn56
BIT 2,(IY+d)FDCBnn57
BIT 3,(IY+d)FDCBnn58
BIT 3,(IY+d)FDCBnn59
BIT 3,(IY+d)FDCBnn5A
BIT 3,(IY+d)FDCBnn5B
BIT 3,(IY+d)FDCBnn5C
BIT 3,(IY+d)FDCBnn5D
BIT 3,(IY+d)FDCBnn5E
BIT 3,(IY+d)FDCBnn5F
BIT 4,(IY+d)FDCBnn60
BIT 4,(IY+d)FDCBnn61
BIT 4,(IY+d)FDCBnn62
BIT 4,(IY+d)FDCBnn63
BIT 4,(IY+d)FDCBnn64
BIT 4,(IY+d)FDCBnn65
BIT 4,(IY+d)FDCBnn66
BIT 4,(IY+d)FDCBnn67
BIT 5,(IY+d)FDCBnn68
BIT 5,(IY+d)FDCBnn69
BIT 5,(IY+d)FDCBnn6A
BIT 5,(IY+d)FDCBnn6B
BIT 5,(IY+d)FDCBnn6C
BIT 5,(IY+d)FDCBnn6D
BIT 5,(IY+d)FDCBnn6E
BIT 5,(IY+d)FDCBnn6F
BIT 6,(IY+d)FDCBnn70
BIT 6,(IY+d)FDCBnn71
BIT 6,(IY+d)FDCBnn72
BIT 6,(IY+d)FDCBnn73
BIT 6,(IY+d)FDCBnn74
BIT 6,(IY+d)FDCBnn75
BIT 6,(IY+d)FDCBnn76
BIT 6,(IY+d)FDCBnn77
BIT 7,(IY+d)FDCBnn78
BIT 7,(IY+d)FDCBnn79
BIT 7,(IY+d)FDCBnn7A
BIT 7,(IY+d)FDCBnn7B
BIT 7,(IY+d)FDCBnn7C
BIT 7,(IY+d)FDCBnn7D
BIT 7,(IY+d)FDCBnn7E
BIT 7,(IY+d)FDCBnn7F
RES B,0,(IY+nn)FDCBnn80
RES C,0,(IY+nn)FDCBnn81
RES D,0,(IY+nn)FDCBnn82
RES E,0,(IY+nn)FDCBnn83
RES H,0,(IY+nn)FDCBnn84
RES L,0,(IY+nn)FDCBnn85
RES 0,(IY+d)FDCBnn86
RES A,0,(IY+nn)FDCBnn87
RES B,1,(IY+nn)FDCBnn88
RES C,1,(IY+nn)FDCBnn89
RES D,1,(IY+nn)FDCBnn8A
RES E,1,(IY+nn)FDCBnn8B
RES H,1,(IY+nn)FDCBnn8C
RES L,1,(IY+nn)FDCBnn8D
RES 1,(IY+d)FDCBnn8E
RES A,1,(IY+nn)FDCBnn8F
RES B,2,(IY+nn)FDCBnn90
RES C,2,(IY+nn)FDCBnn91
RES D,2,(IY+nn)FDCBnn92
RES E,2,(IY+nn)FDCBnn93
RES H,2,(IY+nn)FDCBnn94
RES L,2,(IY+nn)FDCBnn95
RES 2,(IY+d)FDCBnn96
RES A,2,(IY+nn)FDCBnn97
RES B,3,(IY+nn)FDCBnn98
RES C,3,(IY+nn)FDCBnn99
RES D,3,(IY+nn)FDCBnn9A
RES E,3,(IY+nn)FDCBnn9B
RES H,3,(IY+nn)FDCBnn9C
RES L,3,(IY+nn)FDCBnn9D
RES 3,(IY+d)FDCBnn9E
RES A,3,(IY+nn)FDCBnn9F
RES B,4,(IY+nn)FDCBnnA0
RES C,4,(IY+nn)FDCBnnA1
RES D,4,(IY+nn)FDCBnnA2
RES E,4,(IY+nn)FDCBnnA3
RES H,4,(IY+nn)FDCBnnA4
RES L,4,(IY+nn)FDCBnnA5
RES 4,(IY+d)FDCBnnA6
RES A,4,(IY+nn)FDCBnnA7
RES B,5,(IY+nn)FDCBnnA8
RES C,5,(IY+nn)FDCBnnA9
RES D,5,(IY+nn)FDCBnnAA
RES E,5,(IY+nn)FDCBnnAB
RES H,5,(IY+nn)FDCBnnAC
RES L,5,(IY+nn)FDCBnnAD
RES 5,(IY+d)FDCBnnAE
RES A,5,(IY+nn)FDCBnnAF
RES B,6,(IY+nn)FDCBnnB0
RES C,6,(IY+nn)FDCBnnB1
RES D,6,(IY+nn)FDCBnnB2
RES E,6,(IY+nn)FDCBnnB3
RES H,6,(IY+nn)FDCBnnB4
RES L,6,(IY+nn)FDCBnnB5
RES 6,(IY+d)FDCBnnB6
RES A,6,(IY+nn)FDCBnnB7
RES B,7,(IY+nn)FDCBnnB8
RES C,7,(IY+nn)FDCBnnB9
RES D,7,(IY+nn)FDCBnnBA
RES E,7,(IY+nn)FDCBnnBB
RES H,7,(IY+nn)FDCBnnBC
RES L,7,(IY+nn)FDCBnnBD
RES 7,(IY+d)FDCBnnBE
RES A,7,(IY+nn)FDCBnnBF
SET B,0,(IY+nn)FDCBnnC0
SET C,0,(IY+nn)FDCBnnC1
SET D,0,(IY+nn)FDCBnnC2
SET E,0,(IY+nn)FDCBnnC3
SET H,0,(IY+nn)FDCBnnC4
SET L,0,(IY+nn)FDCBnnC5
SET 0,(IY+d)FDCBnnC6
SET A,0,(IY+nn)FDCBnnC7
SET B,1,(IY+nn)FDCBnnC8
SET C,1,(IY+nn)FDCBnnC9
SET D,1,(IY+nn)FDCBnnCA
SET E,1,(IY+nn)FDCBnnCB
SET H,1,(IY+nn)FDCBnnCC
SET L,1,(IY+nn)FDCBnnCD
SET 1,(IY+d)FDCBnnCE
SET A,1,(IY+nn)FDCBnnCF
SET B,2,(IY+nn)FDCBnnD0
SET C,2,(IY+nn)FDCBnnD1
SET D,2,(IY+nn)FDCBnnD2
SET E,2,(IY+nn)FDCBnnD3
SET H,2,(IY+nn)FDCBnnD4
SET L,2,(IY+nn)FDCBnnD5
SET 2,(IY+d)FDCBnnD6
SET A,2,(IY+nn)FDCBnnD7
SET B,3,(IY+nn)FDCBnnD8
SET C,3,(IY+nn)FDCBnnD9
SET D,3,(IY+nn)FDCBnnDA
SET E,3,(IY+nn)FDCBnnDB
SET H,3,(IY+nn)FDCBnnDC
SET L,3,(IY+nn)FDCBnnDD
SET 3,(IY+d)FDCBnnDE
SET A,3,(IY+nn)FDCBnnDF
SET B,4,(IY+nn)FDCBnnE0
SET C,4,(IY+nn)FDCBnnE1
SET D,4,(IY+nn)FDCBnnE2
SET E,4,(IY+nn)FDCBnnE3
SET H,4,(IY+nn)FDCBnnE4
SET L,4,(IY+nn)FDCBnnE5
SET 4,(IY+d)FDCBnnE6
SET A,4,(IY+nn)FDCBnnE7
SET B,5,(IY+nn)FDCBnnE8
SET C,5,(IY+nn)FDCBnnE9
SET D,5,(IY+nn)FDCBnnEA
SET E,5,(IY+nn)FDCBnnEB
SET H,5,(IY+nn)FDCBnnEC
SET L,5,(IY+nn)FDCBnnED
SET 5,(IY+d)FDCBnnEE
SET A,5,(IY+nn)FDCBnnEF
SET B,6,(IY+nn)FDCBnnF0
SET C,6,(IY+nn)FDCBnnF1
SET D,6,(IY+nn)FDCBnnF2
SET E,6,(IY+nn)FDCBnnF3
SET H,6,(IY+nn)FDCBnnF4
SET L,6,(IY+nn)FDCBnnF5
SET 6,(IY+d)FDCBnnF6
SET A,6,(IY+nn)FDCBnnF7
SET B,7,(IY+nn)FDCBnnF8
SET C,7,(IY+nn)FDCBnnF9
SET D,7,(IY+nn)FDCBnnFA
SET E,7,(IY+nn)FDCBnnFB
SET H,7,(IY+nn)FDCBnnFC
SET L,7,(IY+nn)FDCBnnFD
SET 7,(IY+d)FDCBnnFE
SET A,7,(IY+nn)FDCBnnFF
POP IYFDE1nn
EX (SP), IYFDE3nn
PUSH IYFDE5nn
JP (IY)FDE9nn
LD SP, IYFDF9nn
CP nFEnn
RST 7FF

6.3 - Opcode Matrix

Instructions shown in an Opcode Matrix
0123456789ABCDEF
0
NOP 0014
LD BC, nn 01nnnn310
LD (BC), A 0217
INC BC 0316
INC B 0414
DEC B 0514
LD B, n 06nn27
RLCA 0714
EX AF, AF' 0814
ADD HL,BC 09111
LD A, (BC) 0A17
DEC BC 0B16
INC C 0C14
DEC C 0D14
LD C, n 0Enn27
RRCA 0F14
1
DJNZ e 10nn213
LD DE, nn 11nnnn310
LD (DE), A 1217
INC DE 1316
INC D 1414
DEC D 1514
LD D, n 16nn27
RLA 1714
JR e 18nn212
ADD HL,DE 19111
LD A, (DE) 1A17
DEC DE 1B16
INC E 1C14
DEC E 1D14
LD E, n 1Enn27
RRA 1F14
2
JR NZ,e 20nn212
LD HL, nn 21nnnn310
LD (nn), HL 22nnnn316
INC HL 2316
INC H 2414
DEC H 2514
LD H, n 26nn27
DAA 2714
JR Z,e 28nn212
ADD HL,HL 29111
LD HL, (nn) 2Annnn316
DEC HL 2B16
INC L 2C14
DEC L 2D14
LD L, n 2Enn27
CPL 2F14
3
JR NC,e 30nn212
LD SP, nn 31nnnn310
LD (nn), A 32nnnn313
INC SP 3316
INC (HL) 34111
DEC (HL) 35111
LD (HL), n 36nn210
SCF 3714
JR C,e 38nn212
ADD HL,SP 39111
LD A, (nn) 3Annnn313
DEC SP 3B16
INC A 3C14
DEC A 3D14
LD A, n 3Enn27
CCF 3F14
4
LD B, B 4014
LD B, C 4114
LD B, D 4214
LD B, E 4314
LD B, H 4414
LD B, L 4514
LD B, (HL) 4617
LD B, A 4714
LD C, B 4814
LD C, C 4914
LD C, D 4A14
LD C, E 4B14
LD C, H 4C14
LD C, L 4D14
LD C, (HL) 4E17
LD C, A 4F14
5
LD D, B 5014
LD D, C 5114
LD D, D 5214
LD D, E 5314
LD D, H 5414
LD D, L 5514
LD D, (HL) 5617
LD D, A 5714
LD E, B 5814
LD E, C 5914
LD E, D 5A14
LD E, E 5B14
LD E, H 5C14
LD E, L 5D14
LD E, (HL) 5E17
LD E, A 5F14
6
LD H, B 6014
LD H, C 6114
LD H, D 6214
LD H, E 6314
LD H, H 6414
LD H, L 6514
LD H, (HL) 6617
LD H, A 6714
LD L, B 6814
LD L, C 6914
LD L, D 6A14
LD L, E 6B14
LD L, H 6C14
LD L, L 6D14
LD L, (HL) 6E17
LD L, A 6F14
7
LD (HL), B 7017
LD (HL), C 7117
LD (HL), D 7217
LD (HL), E 7317
LD (HL), H 7417
LD (HL), L 7517
HALT 7614
LD (HL), A 7717
LD A, B 7814
LD A, C 7914
LD A, D 7A14
LD A, E 7B14
LD A, H 7C14
LD A, L 7D14
LD A, (HL) 7E17
LD A, A 7F14
8
ADD A,B 8014
ADD A,C 8114
ADD A,D 8214
ADD A,E 8314
ADD A,H 8414
ADD A,L 8514
ADD A,(HL) 8617
ADD A,A 8714
ADC A,B 8814
ADC A,C 8914
ADC A,D 8A14
ADC A,E 8B14
ADC A,H 8C14
ADC A,L 8D14
ADC A,(HL) 8E17
ADC A,A 8F14
9
SUB A,B 9014
SUB A,C 9114
SUB A,D 9214
SUB A,E 9314
SUB A,H 9414
SUB A,L 9514
SUB A,(HL) 9617
SUB A,A 9714
SBC A,B 9814
SBC A,C 9914
SBC A,D 9A14
SBC A,E 9B14
SBC A,H 9C14
SBC A,L 9D14
SBC A,(HL) 9E17
SBC A,A 9F14
A
AND A,B A014
AND A,C A114
AND A,D A214
AND A,E A314
AND A,H A414
AND A,L A514
AND A,(HL) A617
AND A,A A714
XOR A,B A814
XOR A,C A914
XOR A,D AA14
XOR A,E AB14
XOR A,H AC14
XOR A,L AD14
XOR A,(HL) AE17
XOR A,A AF14
B
OR A,B B014
OR A,C B114
OR A,D B214
OR A,E B314
OR A,H B414
OR A,L B514
OR A,(HL) B617
OR A,A B714
CP B B814
CP C B914
CP D BA14
CP E BB14
CP H BC14
CP L BD14
CP (HL) BE17
CP A BF14
C
RET NZ C0111
POP BC C1110
JP NZ,nn C2nnnn310
JP nn C3nnnn310
CALL NZ,nn C4nnnn317
PUSH BC C5111
ADD A,n C6nn27
RST 0 C7111
RET Z C8111
RET C9110
JP Z,nn CAnnnn310
Instruction Prefix CB
CALL Z,nn CCnnnn317
CALL nn CDnnnn317
ADC A,n CEnn27
RST 1 CF111
D
RET NC D0111
POP DE D1110
JP NC,nn D2nnnn310
OUT (n),A D3nn211
CALL NC,nn D4nnnn317
PUSH DE D5111
SUB A,n D6nn27
RST 2 D7111
RET C D8111
EXX D914
JP C,nn DAnnnn310
IN A,(n) DBnn211
CALL C,nn DCnnnn317
Instruction Prefix DD
SBC A,n DEnn27
RST 3 DF111
E
RET PO E0111
POP HL E1110
JP PO,nn E2nnnn310
EX (SP), HL E3119
CALL PO,nn E4nnnn317
PUSH HL E5111
AND A,n E6nn27
RST 4 E7111
RET PE E8111
JP (HL) E914
JP PE,nn EAnnnn310
EX DE, HL EB14
CALL PE,nn ECnnnn317
Instruction Prefix ED
XOR A,n EEnn27
RST 5 EF111
F
RET P F0111
POP AF F1110
JP P,nn F2nnnn310
DI F314
CALL P,nn F4nnnn317
PUSH AF F5111
OR A,n F6nn27
RST 6 F7111
RET N F8111
LD SP, HL F916
JP N,nn FAnnnn310
EI FB14
CALL N,nn FCnnnn317
Instruction Prefix FD
CP n FEnn27
RST 7 FF111
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit Flow Interrupt Special Extension Undefined Undocumented
Opcodes with prefix 0xCB
0123456789ABCDEF
0
RLC B CB00nn28
RLC C CB01nn28
RLC D CB02nn28
RLC E CB03nn28
RLC H CB04nn28
RLC L CB05nn28
RLC (HL) CB06nn28
RLC A CB07nn28
RRC B CB08nn28
RRC C CB09nn28
RRC D CB0Ann28
RRC E CB0Bnn28
RRC H CB0Cnn28
RRC L CB0Dnn28
RRC (HL) CB0Enn215
RRC A CB0Fnn28
1
RL B CB10nn28
RL C CB11nn28
RL D CB12nn28
RL E CB13nn28
RL H CB14nn28
RL L CB15nn28
RL (HL) CB16nn215
RL A CB17nn28
RR B CB18nn28
RR C CB19nn28
RR D CB1Ann28
RR E CB1Bnn28
RR H CB1Cnn28
RR L CB1Dnn28
RR (HL) CB1Enn215
RR A CB1Fnn28
2
SLA B CB20nn28
SLA C CB21nn28
SLA D CB22nn28
SLA E CB23nn28
SLA H CB24nn28
SLA L CB25nn28
SLA (HL) CB26nn215
SLA A CB27nn28
SRA B CB28nn28
SRA C CB29nn28
SRA D CB2Ann28
SRA E CB2Bnn28
SRA H CB2Cnn28
SRA L CB2Dnn28
SRA (HL) CB2Enn215
SRA A CB2Fnn28
3
SLL B CB30
SLL C CB31
SLL D CB32
SLL E CB33
SLL H CB34
SLL L CB35
SLL (HL) CB36
SLL A CB37
SRL B CB38nn28
SRL C CB39nn28
SRL D CB3Ann28
SRL E CB3Bnn28
SRL H CB3Cnn28
SRL L CB3Dnn28
SRL (HL) CB3Enn215
SRL A CB3Fnn28
4
BIT 0,B CB40nn28
BIT 0,C CB41nn28
BIT 0,D CB42nn28
BIT 0,E CB43nn28
BIT 0,H CB44nn28
BIT 0,L CB45nn28
BIT 0,(HL) CB46nn212
BIT 0,A CB47nn28
BIT 1,B CB48nn28
BIT 1,C CB49nn28
BIT 1,D CB4Ann28
BIT 1,E CB4Bnn28
BIT 1,H CB4Cnn28
BIT 1,L CB4Dnn28
BIT 1,(HL) CB4Enn212
BIT 1,A CB4Fnn28
5
BIT 2,B CB50nn28
BIT 2,C CB51nn28
BIT 2,D CB52nn28
BIT 2,E CB53nn28
BIT 2,H CB54nn28
BIT 2,L CB55nn28
BIT 2,(HL) CB56nn212
BIT 2,A CB57nn28
BIT 3,B CB58nn28
BIT 3,C CB59nn28
BIT 3,D CB5Ann28
BIT 3,E CB5Bnn28
BIT 3,H CB5Cnn28
BIT 3,L CB5Dnn28
BIT 3,(HL) CB5Enn212
BIT 3,A CB5Fnn28
6
BIT 4,B CB60nn28
BIT 4,C CB61nn28
BIT 4,D CB62nn28
BIT 4,E CB63nn28
BIT 4,H CB64nn28
BIT 4,L CB65nn28
BIT 4,(HL) CB66nn212
BIT 4,A CB67nn28
BIT 5,B CB68nn28
BIT 5,C CB69nn28
BIT 5,D CB6Ann28
BIT 5,E CB6Bnn28
BIT 5,H CB6Cnn28
BIT 5,L CB6Dnn28
BIT 5,(HL) CB6Enn212
BIT 5,A CB6Fnn28
7
BIT 6,B CB70nn28
BIT 6,C CB71nn28
BIT 6,D CB72nn28
BIT 6,E CB73nn28
BIT 6,H CB74nn28
BIT 6,L CB75nn28
BIT 6,(HL) CB76nn212
BIT 6,A CB77nn28
BIT 7,B CB78nn28
BIT 7,C CB79nn28
BIT 7,D CB7Ann28
BIT 7,E CB7Bnn28
BIT 7,H CB7Cnn28
BIT 7,L CB7Dnn28
BIT 7,(HL) CB7Enn212
BIT 7,A CB7Fnn28
8
RES 0,B CB80nn28
RES 0,C CB81nn28
RES 0,D CB82nn28
RES 0,E CB83nn28
RES 0,H CB84nn28
RES 0,L CB85nn28
RES 0,(HL) CB86nn215
RES 0,A CB87nn28
RES 1,B CB88nn28
RES 1,C CB89nn28
RES 1,D CB8Ann28
RES 1,E CB8Bnn28
RES 1,H CB8Cnn28
RES 1,L CB8Dnn28
RES 1,(HL) CB8Enn215
RES 1,A CB8Fnn28
9
RES 2,B CB90nn28
RES 2,C CB91nn28
RES 2,D CB92nn28
RES 2,E CB93nn28
RES 2,H CB94nn28
RES 2,L CB95nn28
RES 2,(HL) CB96nn215
RES 2,A CB97nn28
RES 3,B CB98nn28
RES 3,C CB99nn28
RES 3,D CB9Ann28
RES 3,E CB9Bnn28
RES 3,H CB9Cnn28
RES 3,L CB9Dnn28
RES 3,(HL) CB9Enn215
RES 3,A CB9Fnn28
A
RES 4,B CBA0nn28
RES 4,C CBA1nn28
RES 4,D CBA2nn28
RES 4,E CBA3nn28
RES 4,H CBA4nn28
RES 4,L CBA5nn28
RES 4,(HL) CBA6nn215
RES 4,A CBA7nn28
RES 5,B CBA8nn28
RES 5,C CBA9nn28
RES 5,D CBAAnn28
RES 5,E CBABnn28
RES 5,H CBACnn28
RES 5,L CBADnn28
RES 5,(HL) CBAEnn215
RES 5,A CBAFnn28
B
RES 6,B CBB0nn28
RES 6,C CBB1nn28
RES 6,D CBB2nn28
RES 6,E CBB3nn28
RES 6,H CBB4nn28
RES 6,L CBB5nn28
RES 6,(HL) CBB6nn215
RES 6,A CBB7nn28
RES 7,B CBB8nn28
RES 7,C CBB9nn28
RES 7,D CBBAnn28
RES 7,E CBBBnn28
RES 7,H CBBCnn28
RES 7,L CBBDnn28
RES 7,(HL) CBBEnn215
RES 7,A CBBFnn28
C
SET 0,B CBC0nn28
SET 0,C CBC1nn28
SET 0,D CBC2nn28
SET 0,E CBC3nn28
SET 0,H CBC4nn28
SET 0,L CBC5nn28
SET 0,(HL) CBC6nn215
SET 0,A CBC7nn28
SET 1,B CBC8nn28
SET 1,C CBC9nn28
SET 1,D CBCAnn28
SET 1,E CBCBnn28
SET 1,H CBCCnn28
SET 1,L CBCDnn28
SET 1,(HL) CBCEnn215
SET 1,A CBCFnn28
D
SET 2,B CBD0nn28
SET 2,C CBD1nn28
SET 2,D CBD2nn28
SET 2,E CBD3nn28
SET 2,H CBD4nn28
SET 2,L CBD5nn28
SET 2,(HL) CBD6nn215
SET 2,A CBD7nn28
SET 3,B CBD8nn28
SET 3,C CBD9nn28
SET 3,D CBDAnn28
SET 3,E CBDBnn28
SET 3,H CBDCnn28
SET 3,L CBDDnn28
SET 3,(HL) CBDEnn215
SET 3,A CBDFnn28
E
SET 4,B CBE0nn28
SET 4,C CBE1nn28
SET 4,D CBE2nn28
SET 4,E CBE3nn28
SET 4,H CBE4nn28
SET 4,L CBE5nn28
SET 4,(HL) CBE6nn215
SET 4,A CBE7nn28
SET 5,B CBE8nn28
SET 5,C CBE9nn28
SET 5,D CBEAnn28
SET 5,E CBEBnn28
SET 5,H CBECnn28
SET 5,L CBEDnn28
SET 5,(HL) CBEEnn215
SET 5,A CBEFnn28
F
SET 6,B CBF0nn28
SET 6,C CBF1nn28
SET 6,D CBF2nn28
SET 6,E CBF3nn28
SET 6,H CBF4nn28
SET 6,L CBF5nn28
SET 6,(HL) CBF6nn215
SET 6,A CBF7nn28
SET 7,B CBF8nn28
SET 7,C CBF9nn28
SET 7,D CBFAnn28
SET 7,E CBFBnn28
SET 7,H CBFCnn28
SET 7,L CBFDnn28
SET 7,(HL) CBFEnn215
SET 7,A CBFFnn28
Opcodes with prefix 0xDD
0123456789ABCDEF
0
ADD IX,BC DD09nn215
1
ADD IX,DE DD19nn215
2
LD IX, nn DD21nnnn414
LD (nn), IX DD22nnnn420
INC IX DD23nn210
INC IXh DD24
DEC IXh DD25
LD IXh,n DD26nn
ADD IX,IX DD29nn215
LD IX, (nn) DD2Annnn420
DEC IX DD2Bnn210
INC IXl DD2C
DEC IXl DD2D
LD IXl,n DD2Enn
3
INC (IX+d) DD34nn323
DEC (IX+d) DD35nn323
LD (IX+d), n DD36nnnn419
ADD IX,SP DD39nn215
4
LD B,IXh DD44
LD B,IXl DD45
LD B, (IX+d) DD46nn319
LD C,IXh DD4C
LD C,IXl DD4D
LD C, (IX+d) DD4Enn319
5
LD D,IXh DD54
LD D,IXl DD55
LD D, (IX+d) DD56nn319
LD E,IXh DD5C
LD E,IXl DD5D
LD E, (IX+d) DD5Enn319
6
LD IXh,B DD60
LD IXh,C DD61
LD IXh,D DD62
LD IXh,E DD63
LD IXh,IHh DD64
LD IXh,IHl DD65
LD H, (IX+d) DD66nn319
LD IXh,A DD67
LD IXl,B DD68
LD IXl,C DD69
LD IXl,D DD6A
LD IXl,E DD6B
LD IXl,IHh DD6C
LD IXl,IHl DD6D
LD L, (IX+d) DD6Enn319
LD IXl,A DD6F
7
LD (IX+d), B DD70nn319
LD (IX+d), C DD71nn319
LD (IX+d), D DD72nn319
LD (IX+d), E DD73nn319
LD (IX+d), H DD74nn319
LD (IX+d), L DD75nn319
LD (IX+d), A DD77nn319
LD A,IXh DD7C
LD A,IXl DD7D
LD A, (IX+d) DD7Enn319
8
ADD A,IXh DD84
ADD A,IXl DD85
ADD A,(IX+d) DD86nn319
ADC A,IXh DD8C
ADC A,IXl DD8D
ADC A,(IX+d) DD8Enn319
9
SUB IXh DD94
SUB IXl DD95
SUB A,(IX+d) DD96nn319
SBC A,IXh DD9C
SBC A,IXl DD9D
SBC A,(IX+d) DD9Enn119
A
AND IXh DDA4
AND IXl DDA5
AND A,(IX+d) DDA6nn319
XOR IXh DDAC
XOR IXl DDAD
XOR A,(IX+d) DDAEnn319
B
OR IXh DDB4
OR IXl DDB5
OR A,(IX+d) DDB6nn319
CP IXh DDBC
CP IXl DDBD
CP (IX+d) DDBEnn319
C
Instruction Prefix DDCB
D
E
POP IX DDE1nn214
EX (SP), IX DDE3nn223
PUSH IX DDE5nn215
JP (IX) DDE9nn28
F
LD SP, IX DDF9nn26
Opcodes with prefix 0xDDCB
0123456789ABCDEF
0
RLC B,(IX+d) DDCBnn00
RLC C,(IX+d) DDCBnn01
RLC D,(IX+d) DDCBnn02
RLC E,(IX+d) DDCBnn03
RLC H,(IX+d) DDCBnn04
RLC L,(IX+d) DDCBnn05
RLC (IX+d) DDCBnn06423
RLC A,(IX+d) DDCBnn07
RRC B,(IX+d) DDCBnn08
RRC C,(IX+d) DDCBnn09
RRC D,(IX+d) DDCBnn0A
RRC E,(IX+d) DDCBnn0B
RRC H,(IX+d) DDCBnn0C
RRC L,(IX+d) DDCBnn0D
RRC (IX+d) DDCBnn0E423
RRC A,(IX+d) DDCBnn0F
1
RL B,(IX+d) DDCBnn10
RL C,(IX+d) DDCBnn11
RL D,(IX+d) DDCBnn12
RL E,(IX+d) DDCBnn13
RL H,(IX+d) DDCBnn14
RL L,(IX+d) DDCBnn15
RL (IX+d) DDCBnn16423
RL A,(IX+d) DDCBnn17
RR B,(IX+d) DDCBnn18
RR C,(IX+d) DDCBnn19
RR D,(IX+d) DDCBnn1A
RR E,(IX+d) DDCBnn1B
RR H,(IX+d) DDCBnn1C
RR L,(IX+d) DDCBnn1D
RR (IX+d) DDCBnn1E423
RR A,(IX+d) DDCBnn1F
2
SLA B,(IX+d) DDCBnn20
SLA C,(IX+d) DDCBnn21
SLA D,(IX+d) DDCBnn22
SLA E,(IX+d) DDCBnn23
SLA H,(IX+d) DDCBnn24
SLA L,(IX+d) DDCBnn25
SLA (IX+d) DDCBnn26423
SLA A,(IX+d) DDCBnn27
SRA B,(IX+d) DDCBnn28
SRA C,(IX+d) DDCBnn29
SRA D,(IX+d) DDCBnn2A
SRA E,(IX+d) DDCBnn2B
SRA H,(IX+d) DDCBnn2C
SRA L,(IX+d) DDCBnn2D
SRA (IX+d) DDCBnn2E423
SRA A,(IX+d) DDCBnn2F
3
SLL B,(IX+d) DDCBnn30
SLL C,(IX+d) DDCBnn31
SLL D,(IX+d) DDCBnn32
SLL E,(IX+d) DDCBnn33
SLL H,(IX+d) DDCBnn34
SLL L,(IX+d) DDCBnn35
SLL (IX+dd) DDCBnn36
SLL A,(IX+d) DDCBnn37
SRL B,(IX+d) DDCBnn38
SRL C,(IX+d) DDCBnn39
SRL D,(IX+d) DDCBnn3A
SRL E,(IX+d) DDCBnn3B
SRL H,(IX+d) DDCBnn3C
SRL L,(IX+d) DDCBnn3D
SRL (IX+d) DDCBnn3E423
SRL A,(IX+d) DDCBnn3F
4
BIT 0,(IX+d) DDCBnn40
BIT 0,(IX+d) DDCBnn41
BIT 0,(IX+d) DDCBnn42
BIT 0,(IX+d) DDCBnn43
BIT 0,(IX+d) DDCBnn44
BIT 0,(IX+d) DDCBnn45
BIT 0,(IX+d) DDCBnn46420
BIT 0,(IX+d) DDCBnn47
BIT 1,(IX+d) DDCBnn48
BIT 1,(IX+d) DDCBnn49
BIT 1,(IX+d) DDCBnn4A
BIT 1,(IX+d) DDCBnn4B
BIT 1,(IX+d) DDCBnn4C
BIT 1,(IX+d) DDCBnn4D
BIT 1,(IX+d) DDCBnn4E420
BIT 1,(IX+d) DDCBnn4F
5
BIT 2,(IX+d) DDCBnn50
BIT 2,(IX+d) DDCBnn51
BIT 2,(IX+d) DDCBnn52
BIT 2,(IX+d) DDCBnn53
BIT 2,(IX+d) DDCBnn54
BIT 2,(IX+d) DDCBnn55
BIT 2,(IX+d) DDCBnn56420
BIT 2,(IX+d) DDCBnn57
BIT 3,(IX+d) DDCBnn58
BIT 3,(IX+d) DDCBnn59
BIT 3,(IX+d) DDCBnn5A
BIT 3,(IX+d) DDCBnn5B
BIT 3,(IX+d) DDCBnn5C
BIT 3,(IX+d) DDCBnn5D
BIT 3,(IX+d) DDCBnn5E420
BIT 3,(IX+d) DDCBnn5F
6
BIT 4,(IX+d) DDCBnn60
BIT 4,(IX+d) DDCBnn61
BIT 4,(IX+d) DDCBnn62
BIT 4,(IX+d) DDCBnn63
BIT 4,(IX+d) DDCBnn64
BIT 4,(IX+d) DDCBnn65
BIT 4,(IX+d) DDCBnn66420
BIT 4,(IX+d) DDCBnn67
BIT 5,(IX+d) DDCBnn68
BIT 5,(IX+d) DDCBnn69
BIT 5,(IX+d) DDCBnn6A
BIT 5,(IX+d) DDCBnn6B
BIT 5,(IX+d) DDCBnn6C
BIT 5,(IX+d) DDCBnn6D
BIT 5,(IX+d) DDCBnn6E420
BIT 5,(IX+d) DDCBnn6F
7
BIT 6,(IX+d) DDCBnn70
BIT 6,(IX+d) DDCBnn71
BIT 6,(IX+d) DDCBnn72
BIT 6,(IX+d) DDCBnn73
BIT 6,(IX+d) DDCBnn74
BIT 6,(IX+d) DDCBnn75
BIT 6,(IX+d) DDCBnn76420
BIT 6,(IX+d) DDCBnn77
BIT 7,(IX+d) DDCBnn78
BIT 7,(IX+d) DDCBnn79
BIT 7,(IX+d) DDCBnn7A
BIT 7,(IX+d) DDCBnn7B
BIT 7,(IX+d) DDCBnn7C
BIT 7,(IX+d) DDCBnn7D
BIT 7,(IX+d) DDCBnn7E420
BIT 7,(IX+d) DDCBnn7F
8
RES B,0,(IX+nn) DDCBnn80
RES C,0,(IX+nn) DDCBnn81
RES D,0,(IX+nn) DDCBnn82
RES E,0,(IX+nn) DDCBnn83
RES H,0,(IX+nn) DDCBnn84
RES L,0,(IX+nn) DDCBnn85
RES 0,(IX+d) DDCBnn86423
RES A,0,(IX+nn) DDCBnn87
RES B,1,(IX+nn) DDCBnn88
RES C,1,(IX+nn) DDCBnn89
RES D,1,(IX+nn) DDCBnn8A
RES E,1,(IX+nn) DDCBnn8B
RES H,1,(IX+nn) DDCBnn8C
RES L,1,(IX+nn) DDCBnn8D
RES 1,(IX+d) DDCBnn8E423
RES A,1,(IX+nn) DDCBnn8F
9
RES B,2,(IX+nn) DDCBnn90
RES C,2,(IX+nn) DDCBnn91
RES D,2,(IX+nn) DDCBnn92
RES E,2,(IX+nn) DDCBnn93
RES H,2,(IX+nn) DDCBnn94
RES L,2,(IX+nn) DDCBnn95
RES 2,(IX+d) DDCBnn96423
RES A,2,(IX+nn) DDCBnn97
RES B,3,(IX+nn) DDCBnn98
RES C,3,(IX+nn) DDCBnn99
RES D,3,(IX+nn) DDCBnn9A
RES E,3,(IX+nn) DDCBnn9B
RES H,3,(IX+nn) DDCBnn9C
RES L,3,(IX+nn) DDCBnn9D
RES 3,(IX+d) DDCBnn9E423
RES A,3,(IX+nn) DDCBnn9F
A
RES B,4,(IX+nn) DDCBnnA0
RES C,4,(IX+nn) DDCBnnA1
RES D,4,(IX+nn) DDCBnnA2
RES E,4,(IX+nn) DDCBnnA3
RES H,4,(IX+nn) DDCBnnA4
RES L,4,(IX+nn) DDCBnnA5
RES 4,(IX+d) DDCBnnA6423
RES A,4,(IX+nn) DDCBnnA7
RES B,5,(IX+nn) DDCBnnA8
RES C,5,(IX+nn) DDCBnnA9
RES D,5,(IX+nn) DDCBnnAA
RES E,5,(IX+nn) DDCBnnAB
RES H,5,(IX+nn) DDCBnnAC
RES L,5,(IX+nn) DDCBnnAD
RES 5,(IX+d) DDCBnnAE423
RES A,5,(IX+nn) DDCBnnAF
B
RES B,6,(IX+nn) DDCBnnB0
RES C,6,(IX+nn) DDCBnnB1
RES D,6,(IX+nn) DDCBnnB2
RES E,6,(IX+nn) DDCBnnB3
RES H,6,(IX+nn) DDCBnnB4
RES L,6,(IX+nn) DDCBnnB5
RES 6,(IX+d) DDCBnnB6423
RES A,6,(IX+nn) DDCBnnB7
RES B,7,(IX+nn) DDCBnnB8
RES C,7,(IX+nn) DDCBnnB9
RES D,7,(IX+nn) DDCBnnBA
RES E,7,(IX+nn) DDCBnnBB
RES H,7,(IX+nn) DDCBnnBC
RES L,7,(IX+nn) DDCBnnBD
RES 7,(IX+d) DDCBnnBE423
RES A,7,(IX+nn) DDCBnnBF
C
SET B,0,(IX+nn) DDCBnnC0
SET C,0,(IX+nn) DDCBnnC1
SET D,0,(IX+nn) DDCBnnC2
SET E,0,(IX+nn) DDCBnnC3
SET H,0,(IX+nn) DDCBnnC4
SET L,0,(IX+nn) DDCBnnC5
SET 0,(IX+d) DDCBnnC6423
SET A,0,(IX+nn) DDCBnnC7
SET B,1,(IX+nn) DDCBnnC8
SET C,1,(IX+nn) DDCBnnC9
SET D,1,(IX+nn) DDCBnnCA
SET E,1,(IX+nn) DDCBnnCB
SET H,1,(IX+nn) DDCBnnCC
SET L,1,(IX+nn) DDCBnnCD
SET 1,(IX+d) DDCBnnCE423
SET A,1,(IX+nn) DDCBnnCF
D
SET B,2,(IX+nn) DDCBnnD0
SET C,2,(IX+nn) DDCBnnD1
SET D,2,(IX+nn) DDCBnnD2
SET E,2,(IX+nn) DDCBnnD3
SET H,2,(IX+nn) DDCBnnD4
SET L,2,(IX+nn) DDCBnnD5
SET 2,(IX+d) DDCBnnD6423
SET A,2,(IX+nn) DDCBnnD7
SET B,3,(IX+nn) DDCBnnD8
SET C,3,(IX+nn) DDCBnnD9
SET D,3,(IX+nn) DDCBnnDA
SET E,3,(IX+nn) DDCBnnDB
SET H,3,(IX+nn) DDCBnnDC
SET L,3,(IX+nn) DDCBnnDD
SET 3,(IX+d) DDCBnnDE423
SET A,3,(IX+nn) DDCBnnDF
E
SET B,4,(IX+nn) DDCBnnE0
SET C,4,(IX+nn) DDCBnnE1
SET D,4,(IX+nn) DDCBnnE2
SET E,4,(IX+nn) DDCBnnE3
SET H,4,(IX+nn) DDCBnnE4
SET L,4,(IX+nn) DDCBnnE5
SET 4,(IX+d) DDCBnnE6423
SET A,4,(IX+nn) DDCBnnE7
SET B,5,(IX+nn) DDCBnnE8
SET C,5,(IX+nn) DDCBnnE9
SET D,5,(IX+nn) DDCBnnEA
SET E,5,(IX+nn) DDCBnnEB
SET H,5,(IX+nn) DDCBnnEC
SET L,5,(IX+nn) DDCBnnED
SET 5,(IX+d) DDCBnnEE423
SET A,5,(IX+nn) DDCBnnEF
F
SET B,6,(IX+nn) DDCBnnF0
SET C,6,(IX+nn) DDCBnnF1
SET D,6,(IX+nn) DDCBnnF2
SET E,6,(IX+nn) DDCBnnF3
SET H,6,(IX+nn) DDCBnnF4
SET L,6,(IX+nn) DDCBnnF5
SET 6,(IX+d) DDCBnnF6423
SET A,6,(IX+nn) DDCBnnF7
SET B,7,(IX+nn) DDCBnnF8
SET C,7,(IX+nn) DDCBnnF9
SET D,7,(IX+nn) DDCBnnFA
SET E,7,(IX+nn) DDCBnnFB
SET H,7,(IX+nn) DDCBnnFC
SET L,7,(IX+nn) DDCBnnFD
SET 7,(IX+d) DDCBnnFE423
SET A,7,(IX+nn) DDCBnnFF
Opcodes with prefix 0xED
0123456789ABCDEF
0
1
2
3
4
IN B,(C) ED40nn212
OUT (C),B ED41nn212
SBC HL,BC ED42nn215
LD (nn), BC ED43nnnn420
NEG ED44nn24
RETN ED45nn214
IM0 ED46nn28
LD I, A ED47nn24
IN C,(C) ED48nn212
OUT (C),C ED49nn212
ADC HL,BC ED4Ann215
LD BC, (nn) ED4Bnnnn420
RETI ED4Dnn214
LD R, A ED4Fnn24
5
IN D,(C) ED50nn212
OUT (C),D ED51nn212
SBC HL,DE ED52nn215
LD (nn), DE ED53nnnn420
IM1 ED56nn28
LD A, I ED57nn29
IN E,(C) ED58nn212
OUT (C),E ED59nn212
ADC HL,DE ED5Ann215
LD DE, (nn) ED5Bnnnn420
IM2 ED5Enn28
LD A, R ED5Fnn29
6
IN H,(C) ED60nn212
OUT (C),H ED61nn212
SBC HL,HL ED62nn215
LD (nn), HL ED63nnnn420
RRD (HL) ED67nn218
IN L,(C) ED68nn212
OUT (C),L ED69nn212
ADC HL,HL ED6Ann215
LD HL, (nn) ED6Bnnnn420
RLD (HL) ED6Fnn218
7
IN F,(C) ED70nn212
OUT (C),F ED71nn212
SBC HL,SP ED72nn215
LD (nn), SP ED73nnnn420
OUT (C),A ED79nn212
ADC HL,SP ED7Ann215
LD SP, (nn) ED7Bnnnn420
8
9
A
LDI EDA0nn216
CPI EDA1nn216
INI EDA2nn216
OUTI EDA3nn216
LDD EDA8nn216
CPD EDA9nn216
IND EDAAnn216
OUTD EDABnn216
B
LDIR EDB0nn221
CPIR EDB1nn221
INIR EDB2nn221
OUTIR EDB3nn221
LDDR EDB8nn221
CPDR EDB9nn221
INDR EDBAnn221
OUTDR EDBBnn221
C
D
E