About the Z80
About the Z80
Table of Contents
The Z80 is an 8-bit microprocessor introduced by Zilog as the startup company's first product.
The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his 11 employees starting in early 1975.
The first working samples were delivered in March 1976, and it was officially introduced on the market in July 1976.
With the revenue from the Z80, the company built its own chip factories and grew to over a thousand employees over the following two
years.
The Zilog Z80 is a software-compatible extension and enhancement of the Intel 8080 and, like it, was mainly aimed at
embedded systems.
Although used in that role, the Z80 also became one of the most widely used CPUs in desktop computers and home computers from the 1970s to the mid-1980s.
It was also common in military applications, musical equipment such as synthesizers (like the Roland Jupiter-8),
and coin operated arcade games of the late 1970s and early 1980s including Pac-Man.
1 - Z80 Registers
About the Registers available on the Z80
The Z80 contains 208 bits of memory that are available to the programmer as registers.
Z80 Registers
| Register Set |
Special Purpose Registers |
| Main |
Alternate |
| Accumulator |
Flags |
Accumulator |
Flags |
Interrupt Vector |
Memory Refresh |
| A |
F |
A' |
F' |
I |
R |
| B |
C |
B' |
C' |
Index Register IX |
Index Register IY |
| D |
E |
D' |
E' |
Stack Pointer SP |
| H |
H |
H' |
L' |
Program Counter PC |
Accumulator and Flag registers
The Z80 provides two independent 8-bit accumulators each with an associated flag register.
The programmer can switch between the two pairs with the
EX AF, AF' instruction.
General Purpose registers
Two matched sets of general purpose registers are available, each set containing six 8-bit registers:
B, C, D, E, H and L.
These registers are also arranged to provide 3 16-bit registers:
BC, DE and HL.
The HL register pair is usually used for addressing memory and has more instructions available to it for
this purpose than BC or DE register pairs.
The programmer can switch between the main (BC, DE and HL) and alternate (BC', DE' and HL') set of general purpose registers with the
EXX instruction.
PC Program Counter
The program counter holds the 16-bit address of the current instruction being fetched from memory.
The Program Counter is automatically incremented after its contents are transferred to the address lines.
When a program jump occurs, the new value is automatically placed in the Program Counter, overriding the incrementer.
SP Stack Pointer
The stack pointer holds the 16-bit address of the current top of a stack located anywhere in external system RAM.
The external stack memory is organized as a last-in first-out (LIFO) file.
Data can be pushed onto the stack using the PUSH instructions
or popped off of the stack using the POP instructions.
2 - Z80 Status Flags
The Flag registers, F and F', supply information to the user about the status of the Z80
CPU at any particular time.
Each of these two Flag registers contains 6 bits of status information that are set or cleared
by CPU operations; bits 3 and 5 are not used.
Four of these bits (C, P/V, Z, and S) can be tested for use with conditional JUMP, CALL, or RETURN instructions.
The H and N flags cannot be tested; these two flags are used for BCD arithmetic.
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| S |
Z |
|
H |
|
P/V |
N |
C |
C Carry
The Carry Flag (C) is set or cleared depending on the operation being performed.
For ADD instructions that generate a Carry, and for SUB instructions that generate a Borrow, the Carry Flag is
set.
The Carry Flag is reset by an ADD instruction that does not generate a Carry, and by a SUB instruction that does
not
generate a Borrow.
This saved Carry facilitates software routines for extended precision arithmetic.
Additionally, the DAA instruction sets the Carry Flag if the conditions for making the decimal adjustment are
met.
For the RLA, RRA, RLS, and RRS instructions, the Carry bit is used as a link between the
least-significant byte (LSB) and the most-significant byte (MSB) for any register or memory location.
During the RLCA, RLC, and SLA instructions, the Carry flag contains the final value shifted out of bit 7 of any
register or memory location.
During the RRCA, RRC, SRA, and SRL instructions, the Carry flag contains the final value shifted out of bit 0 of
any
register or memory location.
For the logical instructions AND, OR, and XOR, the Carry flag is reset.
The Carry flag can also be set by the Set Carry Flag (SCF) instruction and complemented by the Compliment Carry
Flag
(CCF) instruction.
Z Zero
The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the execution of certain instructions is
0.
For 8-bit arithmetic and logical operations, the Z flag is set to a 1 if the resulting byte in the Accumulator
is 0. If the byte is not 0, the Z flag is reset to 0.
For Compare (search) instructions, the Z flag is set to 1 if the value in the Accumulator is equal to the value
in the memory location indicated by the value of the register pair HL.
When testing a bit in a register or memory location, the Z flag contains the complemented state of the indicated
bit.
When inputting or outputting a byte between a memory location and an INI, IND, OUTI, or OUTD I/O device, if the
result of decrementing Register B is 0, then the Z flag is 1; otherwise, the Z flag is 0.
Additionally, for byte inputs from I/O devices using IN r, (C), the Z flag is set to indicate a 0-byte input.
P/V Parity Overflow
The Parity/Overflow (P/V) Flag is set to a specific state depending on the operation being performed.
Overflow
For arithmetic operations, this flag indicates an overflow condition when the result in the Accumulator is
greater than the maximum possible number (+127) or is less than the minimum possible number (–128).
This overflow condition is determined by examining the sign bits of the operands.
For addition, operands with different signs never cause overflow.
When adding operands with similar signs and the result contains a different sign, the Overflow Flag is set.
For subtraction, overflow can occur for operands of unalike signs. Operands of alike signs never cause overflow.
Another method for identifying an overflow is to observe the Carry to and out of the sign bit.
If there is a Carry in and no Carry out, or if there is no Carry in and a Carry out, then an Overflow has
occurred.
Parity
This flag is also used with logical operations and rotate instructions to indicate the resulting parity is even.
The number of 1 bits in a byte are counted.
If the total is Odd, ODD parity is flagged (i.e., P = 0).
If the total is even, even parity is flagged (i.e., P = 1).
When inputting a byte from an I/O device with an IN r, (C) instruction, the P/V Flag is adjusted to indicate
data parity.
Alternate usage
During the CPI, CPIR, CPD, and CPDR search instructions and the LDI, LDIR, LDD, and LDDR block transfer
instructions, the P/V Flag monitors the state of the Byte Count (BC) Register.
When decrementing, if the byte counter decrements to 0, the flag is cleared to 0; otherwise the flag is set to
1.
During the LD A, I and LD A, R instructions, the P/V Flag is set with the value of the interrupt enable
flip-flop (IFF2) for storage or testing.
S Sign
The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7).
When the Z80 CPU performs arithmetic operations on signed numbers, the binary twos-complement notation is used
to represent and process numeric information.
A positive number is identified by a 0 in Bit 7.
A negative number is identified by a 1.
The binary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0
to 127.
A negative number is represented by the twos complement of the equivalent positive number.
The total range for negative numbers is from –1 to –128.
When inputting a byte from an I/O device to a register using an IN r, (C) instruction, the S
Flag indicates either positive (S = 0) or negative (S = 1) data.
N Add/Subtract
The Add/Subtract Flag (N) is used by the Decimal Adjust Accumulator instruction (DAA) to distinguish between the
ADD and SUB instructions.
For ADD instructions, N is cleared to 0.
For SUB instructions, N is set to 1.
H Half Carry
The Half Carry Flag (H) is set (1) or cleared (0) depending on the Carry and Borrow status between bits 3 and 4
of an 8-bit arithmetic operation.
This flag is used by the Decimal Adjust Accumulator (DAA) instruction to correct the result of a packed BCD add
or subtract operation.
For ADD instructions, H is set if a carry occurs from bit 3 to bit 4.
For SUB instructions, H is set if a borrow from bit 4 occurs.
3 - Addresses
The addresses used ny the Z80
The Z80 uses a fixed set of addresses in Page 0 of the address space:
| Address |
Instruction |
Usage |
| 0000 |
RST 0 |
Initial power on |
RST 0 instruction is invoked. |
| RESET pin is held low |
| 0008 |
RST 1 |
RST 1 instruction is invoked.
|
| 0010 |
RST 2 |
RST 2 instruction is invoked.
|
| 0018 |
RST 3 |
RST 3 instruction is invoked.
|
| 0020 |
RST 4 |
RST 4 instruction is invoked.
|
| 0028 |
RST 5 |
RST 5 instruction is invoked.
|
| 0030 |
RST 6 |
RST 6 instruction is invoked.
|
| 0038 |
RST 7 |
RST 7 instruction is invoked. |
| INT Maskable Interrupt handler when in Interrupt Mode 1 |
| 0066 |
|
NMI interrupt handler
|
Addresses 0x0000…0x003F are used by the 8 RST instructions with 8 bytes available for each.
RST 0 is also the start address for when the processor powers on or is reset.
4 - Pin Layout
The physical Z80 processor
General pins
A0…A15 Address Bus
Address Bus (output, active High, tristate).
A0…A15 form a 16-bit Address Bus, which provides the addresses for memory data bus
exchanges (up to 64 KB) and for I/O device exchanges.
D0…D7 Data Bus
D0…D7 constitute an 8-bit bidirectional data bus, used for data exchanges with
memory
and I/O.
CLK Clock (input)
Single-phase MOS-level clock.
System Control
M1 Machine Cycle One (output, active Low)
M1, together with MREQ, indicates that the
current machine cycle is the op code fetch cycle of an instruction execution.
M1, when operating together with IORQ, indicates an interrupt
acknowledge cycle.
MREQ Memory Request (output, active Low, tristate)
MREQ indicates that the address bus holds a valid address for a memory read or a memory
write operation.
IORQ Input/Output Request (output, active Low, tristate)
IORQ indicates that the lower half of the address bus holds a valid I/O address for an
I/O
read or write operation.
IORQ is also generated concurrently with M1 during an
interrupt
acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.
RD Read (output, active Low, tristate)
RD indicates that the CPU wants to read data from memory or an I/O device.
The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.
WR Write (output, active Low, tristate)
WR indicates that the CPU data bus contains valid data to be stored at the
addressed memory or I/O location.
RFSH Refresh (output, active Low)
RFSH, together with MREQ, indicates that the lower seven bits
of
the system’s address bus can be used as a refresh address to the system’s dynamic memories.
Bus Control
BUSACK Bus Acknowledge
The BUSACK pin indicates to the requesting device that the CPU address bus, data bus
and
control signals MREQ, IORQ, RD and
WR
have entered their high-impedance states and other devices on the bus can control those lines.
BUSREQ Bus Request
BUSREQ contains a higher priority than NMI and is always recognized
at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and
control signals MREQ, IORQ, RD and
WR
to enter a high-impedance state so that other devices can control these lines.
BUSREQ is normally wired OR and requires an external pull-up for these applications.
Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from
properly
refreshing dynamic RAM.
CPU Control
HALT HALT State (output, active Low)
HALT indicates that the CPU has executed a HALT instruction and is waiting
for
either a nonmaskable or a maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refreshes.
WAIT WAIT (input, active Low)
WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for
a
data transfer.
The CPU continues to enter a WAIT state as long as this signal is active.
Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.
INT Interrupt Request (input, active Low)
An Interrupt Request is generated by I/O devices.
The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt
enable
flip-flop (IFF) is enabled.
INT is normally wired-OR and requires an external pull-up for these applications.
NMI Nonmaskable Interrupt (input, negative edge-triggered)
NMI contains a higher priority than INT.
NMI is always recognized at the end of the current instruction, independent of the
status
of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066h.
RESET Reset (input, active Low)
RESET initializes the CPU as follows:
- it resets the interrupt enable flip-flop,
- clears the Program Counter and registers I and R,
- sets the interrupt status to Mode 0.
During reset time, the address and data bus enter a high-impedance state, and all control output signals enter
an
inactive state.
RESET must be active for a minimum of three full clock cycles before a reset operation
is
complete.
