Opcodes with bits 7…5 set to 100 are the arithmetic instructions
ADD, ADC, SUB and SBC.
As are those starting with 7…6 set to 11 but ending with bits 2…0 set to 110.
These instructions take an additional numeric operand after the opcode and use that instead of a register as
the source.
Those with 7…5 set to 101 are the logic instructions
AND, XOR, OR and CP.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| Arithmetic with register as source, e.g. ADD A | |||||||
| 1 | 0 | 0 | A | F | r | ||
| Logic with register as source, e.g. OR A | |||||||
| 1 | 0 | 1 | A | F | r | ||
| 8 bit number as source, e.g. SUB 5 | |||||||
| 1 | 1 | X | A | F | 1 | 1 | 0 |
| n | |||||||
| 7 | 6 | 5 | A | F | Instruction | r |
|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0 | 0 | ADC r |
register or 110 = (HL) |
| 1 | ADD r | |||||
| 1 | 0 | SBC r | ||||
| 1 | SUB r | |||||
| 1 | 0 | 0 | AND r | |||
| 1 | XOR r | |||||
| 1 | 0 | OR r | ||||
| 1 | CP r | |||||
| 1 | 0 | 0 | 0 | ADC n | Always set to 110 | |
| 1 | ADD n | |||||
| 1 | 0 | SBC n | ||||
| 1 | SUB n | |||||
| 1 | 0 | 0 | AND n | |||
| 1 | XOR n | |||||
| 1 | 0 | OR n | ||||
| 1 | CP n |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |