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Opcodes

Instruction Set

Table of Contents

Instruction Notation Summary

Notation Description
r Identifies any of the registers A, B, C, D, E, H or L
(HL) Identifies the contents of the memory location whose address is specified by the contents of the HL register pair.
(IX + d) Identifies the contents of the memory location, whose address is specified by the contents of the Index register pair IX plus the signed displacement d
(IY + d) Identifies the contents of the memory location, whose address is specified by the contents of the Index register pair IY plus the signed displacement d
n Identifies a one-byte unsigned integer expression in the range (0 to 255)
nn Identifies a two-byte unsigned integer expression in the range (0 to 65535) (0x0000 to 0xFFFF)
b Identifies a one-byte signed integer expression in the range (-128 to +127)
e Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location
cc Identifies the status of the Flag Register as any of ( NZ, Z, NC, C, PO, PE, P or M ) for the conditional jumps, calls, and return instructions
qq Identifies any of the register pairs BC, DE, HL or AF
ss Identifies any of the register pairs BC, DE, HL or SP
pp Identifies any of the register pairs BC, DE, IX or SP
rr Identifies any of the register pairs BC, DE, IY or SP
s Identifies any of r, n, (HL), (IX+d) or (IY+d)
m Identifies any of r, (HL), (IX+d) or (IY+d)

1 - Load

Load registers, data & memory

1.1 - LD (dd), n

Load number into memory
76543210
 
\((HL) \longleftarrow n\)
LD (HL), n
0011011036
n
 
\(( IX + d ) \longleftarrow n\)
LD (IX+d), n
11011101DD
0011011036
d
n
 
\(( IY + d ) \longleftarrow n\)
LD (IY+d), n
11111101FD
0011011036
d
n
Flags Affected
None.
Opcode Matrix
(HL)(IX+d)(IY+d)
n
LD (HL), n
36nn210
LD (IX+d), n
DD36nnnn419
LD (IY+d), n
FD36nnnn419
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Implicit

1.2 - LD (dd), s

Store register into memory via register
76543210
 
\((BC) \longleftarrow A\)
LD (BC), A
0000001002
 
\((DE) \longleftarrow A\)
LD (DE), A
0001001012
 
\((HL) \longleftarrow r\)
LD (HL), r
01110r
 
\(( IX + d ) \longleftarrow r\)
LD (IX+d), r
11011101DD
01110r
d
 
\(( IY + d ) \longleftarrow r\)
LD (IY+d), r
11111101FD
01110r
d
 
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
None.
Opcode Matrix
ABCDEHL
(HL)
LD (HL), A
7717
LD (HL), B
7017
LD (HL), C
7117
LD (HL), D
7217
LD (HL), E
7317
LD (HL), H
7417
LD (HL), L
7517
(BC)
LD (BC), A
0217






(DE)
LD (DE), A
1217






(IX+d)
LD (IX+d), A
DD77nn319
LD (IX+d), B
DD70nn319
LD (IX+d), C
DD71nn319
LD (IX+d), D
DD72nn319
LD (IX+d), E
DD73nn319
LD (IX+d), H
DD74nn319
LD (IX+d), L
DD75nn319
(IY+d)
LD (IY+d), A
FD77nn319
LD (IY+d), B
FD70nn319
LD (IY+d), C
FD71nn319
LD (IY+d), D
FD72nn319
LD (IY+d), E
FD73nn319
LD (IY+d), H
FD74nn319
LD (IY+d), L
FD75nn319
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

1.3 - LD (nn), s

Store register into memory via address
76543210
 
\((nn) \longleftarrow A\)
LD (nn), A
0011001032
7nn0
158
 
\((nn+1) \longleftarrow dd_h, (nn) \longleftarrow dd_l\)
LD (nn), dd
11101101ED
01dd0011
7nn0
158
 
\((nn+1) \longleftarrow H, (nn) \longleftarrow L\)
LD (nn), HL
0010001022
7nn0
158
 
\((nn+1) \longleftarrow IX_h, (nn) \longleftarrow IX_l\)
LD (nn), IX
11011101DD
0010001022
7nn0
158
 
\((nn+1) \longleftarrow IY_h, (nn) \longleftarrow IY_l\)
LD (nn), IY
11111101FD
0010001022
7nn0
158
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
ABCDEHLIXIYSP
(nn)
LD (nn), A
32nnnn313


LD (nn), HL
22nnnn316



(nn)

LD (nn), BC
ED43nnnn420
LD (nn), DE
ED53nnnn420
LD (nn), HL
ED63nnnn420
LD (nn), IX
DD22nnnn420
LD (nn), IY
FD22nnnn420
LD (nn), SP
ED73nnnn420
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

1.4 - LD A,I and LDA A,R

8-bit register instructions
76543210
 
\(A \longleftarrow I\)
LD A, I
11101101ED
0101011157
 
\(A \longleftarrow R\)
LD A, R
11101101ED
010111115F
Flags Affected
Flags
sz---p/v--
sSet if the source register is negative
zSet if the source register is 0
p/vContains contents of IFF2,
0 if an interrupt occurs during the instruction running
Opcode Matrix
IR
A
LD A, I
ED5729
LD A, R
ED5F29
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

1.5 - LD dd, nn

Load 16-bit number
76543210
 
\(dd \longleftarrow nn\)
LD dd, nn
00dd0001
7nn0
158
 
\(IX \longleftarrow nn\)
LD IX, nn
11011101DD
0010000121
7nn0
158
 
\(IY \longleftarrow nn\)
LD IY, nn
11111101FD
0010000121
7nn0
158
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
BCDEHLIXIYSP
nn
LD BC, nn
01nnnn310
LD DE, nn
11nnnn310
LD HL, nn
21nnnn310
LD IX, nn
DD21nnnn414
LD IY, nn
FD21nnnn414
LD SP, nn
31nnnn310
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Implicit

1.6 - LD r, s

8-bit register instructions
76543210
 
\(r \longleftarrow r'\)
LD r, r'
01rr'
 
\(r \longleftarrow n\)
LD r, n
00r110
n
 
\(A \longleftarrow (BC)\)
LD A, (BC)
000010100A
 
\(A \longleftarrow (DE)\)
LD A, (DE)
000110101A
 
\(r \longleftarrow (HL)\)
LD r, (HL)
01r110
 
\(r \longleftarrow (IX+d)\)
LD r, (IX+d)
11011101DD
01r110
d
 
\(r \longleftarrow (IY+d)\)
LD r, (IY+d)
11111101FD
01r110
d
 
\(I \longleftarrow A\)
 
LD I,A
11101101ED
0100011147
 
\(R \longleftarrow A\)
LD R, A
11101101ED
010011114F
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
None.
Opcode Matrix
ABCDEHL(HL)(BC)(DE)(IX+d)(IY+d)n
A
LD A, A
7F14
LD A, B
7814
LD A, C
7914
LD A, D
7A14
LD A, E
7B14
LD A, H
7C14
LD A, L
7D14
LD A, (HL)
7E17
LD A, (BC)
0A17
LD A, (DE)
1A17
LD A, (IX+d)
DD7Enn319
LD A, (IY+d)
FD7Enn319
LD A, n
3Enn27
B
LD B, A
4714
LD B, B
4014
LD B, C
4114
LD B, D
4214
LD B, E
4314
LD B, H
4414
LD B, L
4514
LD B, (HL)
4617


LD B, (IX+d)
DD46nn319
LD B, (IY+d)
FD46nn319
LD B, n
06nn27
C
LD C, A
4F14
LD C, B
4814
LD C, C
4914
LD C, D
4A14
LD C, E
4B14
LD C, H
4C14
LD C, L
4D14
LD C, (HL)
4E17


LD C, (IX+d)
DD4Enn319
LD C, (IY+d)
FD4Enn319
LD C, n
0Enn27
D
LD D, A
5714
LD D, B
5014
LD D, C
5114
LD D, D
5214
LD D, E
5314
LD D, H
5414
LD D, L
5514
LD D, (HL)
5617


LD D, (IX+d)
DD56nn319
LD D, (IY+d)
FD56nn319
LD D, n
16nn27
E
LD E, A
5F14
LD E, B
5814
LD E, C
5914
LD E, D
5A14
LD E, E
5B14
LD E, H
5C14
LD E, L
5D14
LD E, (HL)
5E17


LD E, (IX+d)
DD5Enn319
LD E, (IY+d)
FD5Enn319
LD E, n
1Enn27
H
LD H, A
6714
LD H, B
6014
LD H, C
6114
LD H, D
6214
LD H, E
6314
LD H, H
6414
LD H, L
6514
LD H, (HL)
6617


LD H, (IX+d)
DD66nn319
LD H, (IY+d)
FD66nn319
LD H, n
26nn27
L
LD L, A
6F14
LD L, B
6814
LD L, C
6914
LD L, D
6A14
LD L, E
6B14
LD L, H
6C14
LD L, L
6D14
LD L, (HL)
6E17


LD L, (IX+d)
DD6Enn319
LD L, (IY+d)
FD6Enn319
LD L, n
2Enn27
I
LD I, A
ED4724












R
LD R, A
ED4F24












Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit Special

1.7 - LD s, (nn)

Load register from memory
76543210
 
\(A \longleftarrow (nn)\)
LD A, (nn)
001110103A
7nn0
158
 
\(H \longleftarrow (nn+1), L \longleftarrow (nn)\)
LD HL, (nn)
001010102A
7nn0
158
 
\(dd_h \longleftarrow (nn+1), dd_l \longleftarrow (nn)\)
LD dd, (nn)
11101101ED
01dd1011
7nn0
158
 
\(IX_h \longleftarrow (nn+1), IX_l \longleftarrow (nn)\)
LD IX, (nn)
11011101DD
001010102A
7nn0
158
 
\(IY_h \longleftarrow (nn+1), IY_l \longleftarrow (nn)\)
LD IY, (nn)
11111101FD
001010102A
7nn0
158
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
ABCDEHLIXIYSP
(nn)
LD A, (nn)
3Annnn313


LD HL, (nn)
2Annnn316



(nn)

LD BC, (nn)
ED4Bnnnn420
LD DE, (nn)
ED5Bnnnn420
LD HL, (nn)
ED6Bnnnn420
LD IX, (nn)
DD2Annnn420
LD IY, (nn)
FD2Annnn420
LD SP, (nn)
ED7Bnnnn420
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

1.8 - LD SP, s

Set Stack Pointer from register
76543210
 
\(SP \longleftarrow HL\)
LD SP,HL
11111001F9
 
\(SP \longleftarrow IX\)
LD SP, IX
11011101DD
11111001F9
 
\(SP \longleftarrow IY\)
LD SP, IY
11111101FD
11111001F9
Flags Affected
None.
Opcode Matrix
HLIXIY
SP
LD SP, HL
F916
LD SP, IX
DDF926
LD SP, IY
FDF926
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

2 - Arithmetic

Arithmetic

2.1 - ADD without carry

Addition without carry

The ADD instruction performs an addition without carry. Any overflow from the addition will be passed on to the carry flag.

2.1.1 - ADD r without carry

Addition of a register without carry
76543210
 
\(A \longleftarrow A + r\)
ADD A, r
10000r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h----
sset if result negative
zset if result is 0
hset if carry from bit 3
Opcode Matrix
ABCDEHL
A
ADD A,A
8714
ADD A,B
8014
ADD A,C
8114
ADD A,D
8214
ADD A,E
8314
ADD A,H
8414
ADD A,L
8514
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

2.1.2 - ADD n without carry

Addition of a number without carry
76543210
 
\(A \longleftarrow A + n\)
ADD A, n
11000110C6
n
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if overflow
cset if carry from bit 7
Opcode Matrix
n
A
ADD A,n
C6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Implicit

2.1.3 - ADD (dd) without carry

Addition of memory without carry
76543210
 
\(A \longleftarrow A + (HL)\)
ADD A, (HL)
1000011086
 
\(A \longleftarrow A + (IX+d)\)
ADD A, (IX+d)
11011101DD
1000011086
d
 
\(A \longleftarrow A + (IY+d)\)
ADD A, (IY+d)
11111101FD
1000011086
d
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if overflow
cset if carry from bit 7
Opcode Matrix
(HL)(IX+d)(IY+d)
A
ADD A,(HL)
8617
ADD A,(IX+d)
DD86nn319
ADD A,(IY+d)
FD86nn319
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

2.1.4 - ADD ss to HL without carry

Addition without carry
76543210
 
\(HL \longleftarrow HL + dd\)
ADD HL, dd
00dd1001
 
\(IX \longleftarrow IX + pp\)
ADD IX, pp
11011101DD
00pp1001
 
\(IY \longleftarrow IY + mm\)
ADD IY, mm
11111101FD
00mm1001
Registers
Valueddmmpp
00BCBCBC
01DEDEDE
10HLIYIX
11SPSPSP
Flags Affected
Flags
sz-h---c
sset if result negative
zset if result is 0
hset if carry from bit 11
cset if carry from bit 15
Opcode Matrix
BCDEHLSPIXIY
HL
ADD HL,BC
09111
ADD HL,DE
19111
ADD HL,HL
29111
ADD HL,SP
39111


IX
ADD IX,BC
DD09215
ADD IX,DE
DD19215

ADD IX,SP
DD39215
ADD IX,IX
DD29215

IY
ADD IY,BC
FD09215
ADD IY,DE
FD19215

ADD IY,SP
FD39215

ADD IY,IY
FD29215
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

2.2 - ADC Add with Carry

Addition with carry

The ADC instruction performs an addition with carry. If carry is set then it will be included in the calculation whilst any overflow from the addition will be passed on to the carry flag.

2.2.1 - ADC 8 bit add with Carry

Addition with carry
76543210
 
\(A \longleftarrow A + r + Carry\)
ADC A,r
10001r
 
\(A \longleftarrow A + n + Carry\)
ADC A,n
11001110CE
n
 
\(A \longleftarrow A + (HL) + Carry\)
ADC A, (HL)
100011108E
 
\(A \longleftarrow A + (IX+d) + Carry\)
ADC A, (IX + d)
11011101DD
100011108E
d
 
\(A \longleftarrow A + (IY+d) + Carry\)
ADC A, (IY + d)
11111101FD
100011108E
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if overflow
cset if carry from bit 7
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
ADC A,A
8F14
ADC A,B
8814
ADC A,C
8914
ADC A,D
8A14
ADC A,E
8B14
ADC A,H
8C14
ADC A,L
8D14
ADC A,(HL)
8E17
ADC A,(IX+d)
DD8Enn319
ADC A,(IY+d)
FD8Enn319
ADC A,n
CEnn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

2.2.2 - ADC 16 bit add with Carry

Addition with carry
76543210
 
\(HL \longleftarrow HL + ss + Carry\)
ADC HL, dd
11101101ED
01dd1010
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if carry from bit 11
p/vset if overflow
cset if carry from bit 15
Opcode Matrix
BCDEHLSP
HL
ADC HL,BC
ED4A215
ADC HL,DE
ED5A215
ADC HL,HL
ED6A215
ADC HL,SP
ED7A215
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

2.3 - SUB Subtract without Carry

Subtraction without Carry

\(A \longleftarrow A - s\)

This s operand is any of r, n, (HL), (IX+d), or (IY+d).

These possible op code/operand combinations are assembled as follows in the object code:

76543210
 
SUB r
10010r
 
SUB n
11010110D6
n
 
SUB (HL)
1001011096
 
SUB (IX+d)
11011101DD
1001011096
d
 
SUB (IX+d)
11111101FD
1001011096
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if overflow
cset if borrow
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
SUB A,A
9714
SUB A,B
9014
SUB A,C
9114
SUB A,D
9214
SUB A,E
9314
SUB A,H
9414
SUB A,L
9514
SUB A,(HL)
9617
SUB A,(IX+d)
DD96nn319
SUB A,(IY+d)
FD96nn319
SUB A,n
D6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

2.4 - SBC Subtract with Carry

Subtraction with Carry
76543210
 
\(A \longleftarrow A - r - Carry\)
SBC A, r
10011r
 
\(A \longleftarrow A - n - Carry\)
SBC A,n
11011110DE
 
\(A \longleftarrow A - (HL) - Carry\)
SBC A, (HL)
100111109E
 
\(A \longleftarrow A - (IX+d) - Carry\)
SBC A, (IX+d)
11011101DD
100111109E
d
 
\(A \longleftarrow A - (IY+d) - Carry\)
SBC A, (IY+d)
11111101FD
100111109E
d
 
\(A \longleftarrow A - ss - Carry\)
SBC HL, ss
11101101ED
01dd0010
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if overflow
cset if borrow
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)nBCDEHLSP
A
SBC A,A
9F14
SBC A,B
9814
SBC A,C
9914
SBC A,D
9A14
SBC A,E
9B14
SBC A,H
9C14
SBC A,L
9D14
SBC A,(HL)
9E17
SBC A,(IX+d)
DD9Enn119
SBC A,(IY+d)
FD9Enn119
SBC A,n
DEnn27




HL











SBC HL,BC
ED42215
SBC HL,DE
ED52215
SBC HL,HL
ED62215
SBC HL,SP
ED72215
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

2.5 - AND

Binary AND

\(A \longleftarrow A \land s\)

76543210
 
AND r
10100r
 
AND n
11100110E6
n
 
AND(HL)
10100110A6
 
AND (IX+d)
11011101DD
10100110A6
d
 
AND (IY+d)
11111101FD
10100110A6
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset
p/vset if overflow
creset
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
AND A,A
A714
AND A,B
A014
AND A,C
A114
AND A,D
A214
AND A,E
A314
AND A,H
A414
AND A,L
A514
AND A,(HL)
A617
AND A,(IX+d)
DDA6nn319
AND A,(IY+d)
FDA6nn319
AND A,n
E6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

2.6 - OR

Binary OR

\(A \longleftarrow A \lor s\)

76543210
 
OR r
10110r
 
OR n
11110110F6
n
 
OR (HL)
10110110B6
 
OR (IX+d)
11011101DD
10110110B6
d
 
OR (IY+d)
11111101FD
10110110B6
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if overflow
creset
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
OR A,A
B714
OR A,B
B014
OR A,C
B114
OR A,D
B214
OR A,E
B314
OR A,H
B414
OR A,L
B514
OR A,(HL)
B617
OR A,(IX+d)
DDB6nn319
OR A,(IY+d)
FDB6nn319
OR A,n
F6nn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

2.7 - XOR

Binary Exclusive OR

\(A \longleftarrow A \oplus s\)

76543210
 
XOR r
10101r
 
XOR n
11101110EE
n
 
XOR (HL)
10101110AE
 
XOR (IX+d)
11011101DD
10101110AE
d
 
XOR (IY+d)
11111101FD
10101110AE
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if overflow
creset
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
A
XOR A,A
AF14
XOR A,B
A814
XOR A,C
A914
XOR A,D
AA14
XOR A,E
AB14
XOR A,H
AC14
XOR A,L
AD14
XOR A,(HL)
AE17
XOR A,(IX+d)
DDAEnn319
XOR A,(IY+d)
FDAEnn319
XOR A,n
EEnn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

2.8 - INC Increment

Increment by 1

INC increments either an 8-bit register or an 16-bit register pair.

2.8.1 - INC 8-bit Increment

Increment 8-bit register by 1
76543210
 
\(s \longleftarrow r + 1\)
INC r
00r100
 
\((HL) \longleftarrow (HL) + 1\)
INC (HL)
0011010034
 
\((IX+d) \longleftarrow (IX+d) + 1\)
INC (IX+d)
11011101DD
0011010034
d
 
\((IY+d) \longleftarrow (IY+d) + 1\)
INC (IY+d)
11111101FD
0011010034
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hset if carry from bit 3
p/vset if register was 0x7F before operation, reset otherwise
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
Op
INC A
3C14
INC B
0414
INC C
0C14
INC D
1414
INC E
1C14
INC H
2414
INC L
2C14
INC (HL)
34111
INC (IX+d)
DD34nn323
INC (IY+d)
FD34nn323
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

2.8.2 - INC 16-bit Increment

Increment 16-bit register pair by 1
76543210
 
\(dd \longleftarrow dd + 1\)
INC qq
00dd0011
 
\(IX \longleftarrow IX + 1\)
INC IX
11011101DD
0010001123
 
\(IY \longleftarrow IY + 1\)
INC IY
11111101FD
0010001123
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
BCDEHLSPIXIY
Op
INC BC
0316
INC DE
1316
INC HL
2316
INC SP
3316
INC IX
DD23210
INC IY
FD23210
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

2.9 - DEC Decrement

Decrement

DEC decrements either an 8-bit register or an 16-bit register pair.

2.9.1 - DEC 8-bit Decrement

Decrement
76543210
 
\(r \longleftarrow r - 1\)
DEC r
00r101
 
\((HL) \longleftarrow (HL) - 1\)
DEC (HL)
00110101
 
\((IX+d) \longleftarrow (IX+d) - 1\)
DEC (IX+d)
11011101DD
0011010135
d
 
\((IY+d) \longleftarrow (IY+d) - 1\)
DEC (IY+d)
11111101FD
0011010135
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if register was 0x80 before operation, reset otherwise
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
Op
DEC A
3D14
DEC B
0514
DEC C
0D14
DEC D
1514
DEC E
1D14
DEC H
2514
DEC L
2D14
DEC (HL)
35111
DEC (IX+d)
DD35nn323
DEC (IY+d)
FD35nn323
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

2.9.2 - DEC 16-bit Decrement

Decrement 16-bit register pair
76543210
 
\(dd \longleftarrow dd - 1\)
DEC dd
00dd1011
 
\(IX \longleftarrow IX - 1\)
DEC IX
11011101DD
001010112B
 
\(IY \longleftarrow IY - 1\)
DEC IY
11111101FD
001010112B
Registers
Valuedd
00BC
01DE
10HL
11SP
Flags Affected
None.
Opcode Matrix
BCDEHLSPIXIY
Op
DEC BC
0B16
DEC DE
1B16
DEC HL
2B16
DEC SP
3B16
DEC IX
DD2B210
DEC IY
FD2B210
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

2.10 - CP

Comparison

\(A - s\)

76543210
 
CP r
10111r
 
CP n
11111110FE
n
 
CP (HL)
10111110BE
 
CP (IX+d)
11011101DD
10111110BE
d
 
CP (IY+d)
11111101FD
10111110BE
d
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hset if borrow from bit 4
p/vset if overflow
cset if borrow
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)n
Op
CP A
BF14
CP B
B814
CP C
B914
CP D
BA14
CP E
BB14
CP H
BC14
CP L
BD14
CP (HL)
BE17
CP (IX+d)
DDBEnn319
CP (IY+d)
FDBEnn319
CP n
FEnn27
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory Implicit

3 - Program Flow

Jump, Call and Return

3.1 - Jump absolute

76543210
 
\(PC \longleftarrow nn\)
JP nn
11000011C3
7nn0
158
 
\(\begin{rcases} PC \longleftarrow nn \end{rcases} \text {if } ccc = true\)
11ccc010
7nn0
158
 
\(PC \longleftarrow HL\)
JP (HL)
11101001E9
 
\(PC \longleftarrow IX\)
JP (IX)
11011101DD
11101001E9
 
\(PC \longleftarrow IY\)
JP (IY)
11111101FD
11101001E9
Conditions
cccAbbrev Condition Flag
000NZ Non Zero Z
001Z Zero
010NC No Carry C
011C Carry
100 PO Parity Odd P/V
101 PE Parity Even
110 P Sign Positive S
111 M Sign Negative

Jumps to 16bit registers

Although the instruction JP (HL) looks like it's using indirect addressing, it doesn't. It takes the address in HL as the new PC, so it should be read as if it's JP HL.

The same applies for JP (IX) and JP (IY) - the actual register is used not the value at that address.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZPEPONP
JP nn
JP nn
C3nnnn310
JP C,nn
DAnnnn310
JP NC,nn
D2nnnn310
JP Z,nn
CAnnnn310
JP NZ,nn
C2nnnn310
JP PE,nn
EAnnnn310
JP PO,nn
E2nnnn310
JP N,nn
FAnnnn310
JP P,nn
F2nnnn310
JP (HL)
JP (HL)
E914








JP (IX)
JP (IX)
DDE928








JP (IY)
JP (IY)
FDE928








Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.2 - Jump Relative

76543210
 
\(PC \longleftarrow PC + e\)
JR e
0001100018
e-2
 
\(\begin{rcases} PC \longleftarrow (PC) + e \end{rcases} \text {if } cc = true\)
JR cc, e
001cc000
e-2
 
\(B \longleftarrow B - 1\\ \begin{rcases} PC \longleftarrow PC + e \end{rcases} \text{ if } B \not = 0\)
DJNZ e
0001000010
e-2
Conditions
ccAbbrev Condition Flag
00NZ Non Zero Z
01Z Zero
10NC No Carry C
11C Carry

Relative Jumps

For relative instructions the offset is taken from the address of the op code so is in the range -126 to 129. Assemblers usually account for the difference where the value in memory is e-2.

Timing

For JR then when a jump takes place then it takes 12(4,3,5) T-States whilst no jump 7(4,3) T-States.

For DJNZ if the jump takes place then it takes 13 (5,3,5) T-States. If no jump then 8 (5,3) T-States.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZB!=0
JR e
JR e
18nn212
JR C,e
38nn212
JR NC,e
30nn212
JR Z,e
28nn212
JR NZ,e
20nn212

DJNZ e





DJNZ e
10nn213
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.3 - Call subroutine

76543210
 
\((SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn\)
CALL nn
11001101CD
7nn0
158
 
\(\begin{rcases} (SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn \end{rcases} \text{ if } ccc = true\)
CALL ccc, nn
11ccc100CD
7nn0
158
Conditions
cccAbbrev Condition Flag
000NZ Non Zero Z
001Z Zero
010NC No Carry C
011C Carry
100 PO Parity Odd P/V
101 PE Parity Even
110 P Sign Positive S
111 M Sign Negative

Timing

All call operation's take 17 (4,3,4,3,3) T-States, except for the conditional ones when the condition has not been met. In those instances it takes 10(4,3,3) T-States.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZPEPONP
CALL nn
CALL nn
CDnnnn317
CALL C,nn
DCnnnn317
CALL NC,nn
D4nnnn317
CALL Z,nn
CCnnnn317
CALL NZ,nn
C4nnnn317
CALL PE,nn
ECnnnn317
CALL PO,nn
E4nnnn317
CALL N,nn
FCnnnn317
CALL P,nn
F4nnnn317
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.4 - Return from Subroutine

76543210
 
\(PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2\)
RET
11001001
 
\(\begin{rcases} PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2 \end{rcases} \text{ if } ccc = true\)
RET ccc
11ccc000
Conditions
cccAbbrev Condition Flag
000NZ Non Zero Z
001Z Zero
010NC No Carry C
011C Carry
100 PO Parity Odd P/V
101 PE Parity Even
110 P Sign Positive S
111 M Sign Negative

Timing

The unconditional RET takes 10 (4,3,3) T-States. The conditional RET takes 17(5,3,3) T-States if the condition is true and 5 T-States if false and no return was performed.

Flags Affected
None.
Opcode Matrix
UncondCNCZNZPEPONP
RET
RET
C9110
RET C
D8111
RET NC
D0111
RET Z
C8111
RET NZ
C0111
RET PE
E8111
RET PO
E0111
RET N
F8111
RET P
F0111
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Flow

3.5 - RST

Invoke a Reset

RST performs a reset. Specifically it calls a routine at one of 8 addresses at the base of memory. It is the equivalent of performing a CALL to that address except the RST instruction is just 1 byte compared to 3 for CALL and is slightly faster.

\((SP-1) \longleftarrow PC_h \\(SP-2) \longleftarrow PC_l \\SP \longleftarrow SP-2 \\PC_h \longleftarrow 0\\PC_l \longleftarrow b*8\)

76543210
11b111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Issues with RST instructions

Assemblers use different conventions for the RST instruction. Some use numbers 0…7 whilst others use the address of the code invoked. They are all equivalent, as there are just 8 possible instruction codes.

Address OP Code RST Instruction Action
0000 C7 RST 0 Reset machine
0008 CF RST 1 RST 8 Operating System Specific
0010 D7 RST 2 RST $10 RST 16
0018 DF RST 3 RST $18 RST 24
0020 E7 RST 4 RST $20 RST 32
0028 EF RST 5 RST $28 RST 40
0030 F7 RST 6 RST $30 RST 48
0038 FF RST 7 RST $38 RST 56 Interrupt Handler in Mode 1
Flags Affected
None.
Opcode Matrix
Reset routine
01234567
RST
RST 0
C7111
RST 1
CF111
RST 2
D7111
RST 3
DF111
RST 4
E7111
RST 5
EF111
RST 6
F7111
RST 7
FF111
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

3.6 - Return from Interrupt

76543210
 
\(PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2\)
RETI
11101101ED
010011014D
 
\(PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2 \\ IFF_1 \longleftarrow IFF_2\)
RETN
11101101ED
0100010145
Flags Affected
None.
Opcode Matrix
RETIRETN
Op
RETI
ED4D214
RETN
ED45214
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Interrupt

4 - Stack

Push Pull onto the stack
76543210
 
\((SP-2) \longleftarrow qq_l, (SP-1) \longleftarrow qq_h\)
PUSH qq
11qq0101
 
\((SP-2) \longleftarrow IX_l, (SP-1) \longleftarrow IX_h\)
PUSH IX
11011101DD
11100101E5
 
\((SP-2) \longleftarrow IY_l, (SP-1) \longleftarrow IY_h\)
PUSH IY
11111101FD
11100101E5
 
\(qq_h \longleftarrow (SP-1), qq_l \longleftarrow (SP)\)
POP qq
11qq0001
 
\(IX_h \longleftarrow (SP-1), IX_l \longleftarrow (SP)\)
POP IX
11011101DD
11100001E1
 
\(IY_h \longleftarrow (SP-1), IY_l \longleftarrow (SP)\)
POP IY
11111101FD
11100001E1
Registers
Valueqq
00BC
01DE
10HL
11AF
Flags Affected
None.
Opcode Matrix
AFBCDEHLIXIY
PUSH
PUSH AF
F5111
PUSH BC
C5111
PUSH DE
D5111
PUSH HL
E5111
PUSH IX
DDE5215
PUSH IY
FDE5215
POP
POP AF
F1110
POP BC
C1110
POP DE
D1110
POP HL
E1110
POP IX
DDE1214
POP IY
FDE1214
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

5 - Rotate and Shift

Rotate Shift instructions

5.1 - RL Rotate bits left with Carry

Rotate bits left with carry
Visualisation of the RLA instruction
76543210
 
RLA
0001011117
 
RL r
11001011CB
00010r
 
RL (HL)
11001011CB
0001011016
 
RL (IX+d)
11011101DD
11001011CB
d
0001011016
 
RL (IY+d)
11111101FD
11001011CB
d
0001011016
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 7 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RL
RLA
1714









RL
RL A
CB1728
RL B
CB1028
RL C
CB1128
RL D
CB1228
RL E
CB1328
RL H
CB1428
RL L
CB1528
RL (HL)
CB16215
RL (IX+d)
DDCBnn16423
RL (IY+d)
FDCBnn16423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

5.2 - RLC Rotate bits left with Carry

Rotate bits left with carry
Visualisation of the RLC instruction
76543210
 
RLCA
0000011107
 
RLC r
11001011CB
00000r
 
RLC (HL)
11001011CB
0000011006
 
RLC (IX+d)
11011101DD
11001011CB
d
0000011006
 
RLC (IY+d)
11111101FD
11001011CB
d
0000011006
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 7 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RLC
RLCA
0714









RLC
RLC A
CB0728
RLC B
CB0028
RLC C
CB0128
RLC D
CB0228
RLC E
CB0328
RLC H
CB0428
RLC L
CB0528
RLC (HL)
CB0628
RLC (IX+d)
DDCBnn06423
RLC (IY+d)
FDCBnn06423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

5.3 - RR Rotate bits right with Carry

Rotate bits right with carry
Visualisation of the RRA instruction
76543210
 
RRA
000111111F
 
RR r
11001011CB
00011r
 
RR (HL)
11001011CB
000111101E
 
RR(IX+d)
11011101DD
11001011CB
d
000111101E
 
RR (IY+d)
11111101FD
11001011CB
d
000111101E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RR
RRA
1F14









RR
RR A
CB1F28
RR B
CB1828
RR C
CB1928
RR D
CB1A28
RR E
CB1B28
RR H
CB1C28
RR L
CB1D28
RR (HL)
CB1E215
RR (IX+d)
DDCBnn1E423
RR (IY+d)
FDCBnn1E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

5.4 - RRC Rotate bits right with Carry

Rotate bits left with carry
Visualisation of the RRC instruction
76543210
 
RRCA
000011110F
 
RRC r
11001011CB
00001r
 
RRC (HL)
11001011CB
000011100E
 
RRC (IX+d)
11011101DD
11001011CB
d
000011100E
 
RRC (IY+d)
11111101FD
11001011CB
d
000011100E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
RRC
RRCA
0F14









RRC
RRC A
CB0F28
RRC B
CB0828
RRC C
CB0928
RRC D
CB0A28
RRC E
CB0B28
RRC H
CB0C28
RRC L
CB0D28
RRC (HL)
CB0E215
RRC (IX+d)
DDCBnn0E423
RRC (IY+d)
FDCBnn0E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

5.5 - SLA Shift bits left with Carry

Shift bits left with carry
Visualisation of the SLA instruction
76543210
 
SLA r
11001011CB
00100r
 
SLA (HL)
11001011CB
0010011026
 
SLA (IX+d)
11011101DD
11001011CB
d
0010011026
 
SLA (IY+d)
11111101FD
11001011CB
d
0010011026
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 7 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
SLA
SLA A
CB2728
SLA B
CB2028
SLA C
CB2128
SLA D
CB2228
SLA E
CB2328
SLA H
CB2428
SLA L
CB2528
SLA (HL)
CB26215
SLA (IX+d)
DDCBnn26423
SLA (IY+d)
FDCBnn26423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

5.6 - SRA Rotate bits right with Carry

Rotate bits right with carry, bit 7 remains unchanged
Visualisation of the SRA instruction

An arithmetic shift right 1 bit position is performed on the contents of operand. The contents of bit 0 are copied to the Carry flag and the previous contents of bit 7 remain unchanged.

76543210
 
SRA r
11001011CB
00101r
 
SRA (HL)
11001011CB
001011102E
 
SRA (IX+d)
11011101DD
11001011CB
d
001011102E
 
SRA (IY+d)
11111101FD
11001011CB
d
001011102E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
SRA
SRA A
CB2F28
SRA B
CB2828
SRA C
CB2928
SRA D
CB2A28
SRA E
CB2B28
SRA H
CB2C28
SRA L
CB2D28
SRA (HL)
CB2E215
SRA (IX+d)
DDCBnn2E423
SRA (IY+d)
FDCBnn2E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

5.7 - SRL Rotate bits right with Carry

Rotate bits right with carry, bit 7 is reset
Visualisation of the SRL instruction
76543210
 
SRL r
11001011CB
00111r
 
SRL (HL)
11001011CB
001111103E
 
SRL (IX+d)
11011101DD
11001011CB
d
001111103E
 
SRL (IY+d)
11111101FD
11001011CB
d
001111103E
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Flags Affected
Flags
sz-h-p/v-c
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
cdata from bit 0 of source register
Opcode Matrix
ABCDEHL(HL)(IX+d)(IY+d)
SRL
SRL A
CB3F28
SRL B
CB3828
SRL C
CB3928
SRL D
CB3A28
SRL E
CB3B28
SRL H
CB3C28
SRL L
CB3D28
SRL (HL)
CB3E215
SRL (IX+d)
DDCBnn3E423
SRL (IY+d)
FDCBnn3E423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

5.8 - RLD

Rotate bit pairs in A and (HL) left
Visualisation of the RLD instruction
76543210
11101101ED
011011116F

The contents of the low-order four bits (bits 3, 2, 1, and 0) of the memory location (HL) are copied to the high-order four bits (7, 6, 5, and 4) of that same memory location; the previous contents of those high-order four bits are copied to the low-order four bits of the Accumulator (Register A); and the previous contents of the low-order four bits of the Accumulator are copied to the low-order four bits of memory location (HL). The contents of the high-order bits of the Accumulator are unaffected.

Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
Opcode Matrix
(HL)
Op
RLD (HL)
ED6F218
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

5.9 - RRD

Rotate bit pairs in A and (HL) right
Visualisation of the RRD instruction
76543210
11101101ED
0110011167

The contents of the low-order four bits (bits 3, 2, 1, and 0) of memory location (HL) are copied to the low-order four bits of the Accumulator (Register A). The previous contents of the low-order four bits of the Accumulator are copied to the high-order four bits (7, 6, 5, and 4) of location (HL); and the previous contents of the high-order four bits of (HL) are copied to the low-order four bits of (HL). The contents of the high-order bits of the Accumulator are unaffected.

Flags Affected
Flags
sz-h-p/v--
sset if result negative
zset if result is 0
hreset
p/vset if parity even, reset if parity odd
Opcode Matrix
(HL)
Op
RRD (HL)
ED67218
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

6 - Bit Manipulation

Bit Manipulation instructions

6.1 - BIT

Test if a specific bit is set
76543210
 
\(Z \longleftarrow \overline{r_b}\)
BIT b, r
11001011CB
01br
 
\(Z \longleftarrow \overline{(HL)_b}\)
BIT b, (HL)
11001011CB
01b110
 
\(Z \longleftarrow \overline{(IX+d)_b}\)
BIT b, (IX+d)
11011101DD
11001011CB
d
01b110
 
\(Z \longleftarrow \overline{(IY+d)_b}\)
BIT b, (IY+d)
11111101FD
11001011CB
d
01b110
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

Flags Affected
Flags
-z-h--n-
zset if the specified bit is 0
hset
nreset
Opcode Matrix
Source
ABCDEHL(HL)(IX+d)(IY+d)
BIT 0
BIT 0,A
CB4728
BIT 0,B
CB4028
BIT 0,C
CB4128
BIT 0,D
CB4228
BIT 0,E
CB4328
BIT 0,H
CB4428
BIT 0,L
CB4528
BIT 0,(HL)
CB46212
BIT 0,(IX+d)
DDCBnn46420
BIT 0,(IY+d)
FDCBnn46420
BIT 1
BIT 1,A
CB4F28
BIT 1,B
CB4828
BIT 1,C
CB4928
BIT 1,D
CB4A28
BIT 1,E
CB4B28
BIT 1,H
CB4C28
BIT 1,L
CB4D28
BIT 1,(HL)
CB4E212
BIT 1,(IX+d)
DDCBnn4E420
BIT 1,(IY+d)
FDCBnn4E420
BIT 2
BIT 2,A
CB5728
BIT 2,B
CB5028
BIT 2,C
CB5128
BIT 2,D
CB5228
BIT 2,E
CB5328
BIT 2,H
CB5428
BIT 2,L
CB5528
BIT 2,(HL)
CB56212
BIT 2,(IX+d)
DDCBnn56420
BIT 2,(IY+d)
FDCBnn56420
BIT 3
BIT 3,A
CB5F28
BIT 3,B
CB5828
BIT 3,C
CB5928
BIT 3,D
CB5A28
BIT 3,E
CB5B28
BIT 3,H
CB5C28
BIT 3,L
CB5D28
BIT 3,(HL)
CB5E212
BIT 3,(IX+d)
DDCBnn5E420
BIT 3,(IY+d)
FDCBnn5E420
BIT 4
BIT 4,A
CB6728
BIT 4,B
CB6028
BIT 4,C
CB6128
BIT 4,D
CB6228
BIT 4,E
CB6328
BIT 4,H
CB6428
BIT 4,L
CB6528
BIT 4,(HL)
CB66212
BIT 4,(IX+d)
DDCBnn66420
BIT 4,(IY+d)
FDCBnn66420
BIT 5
BIT 5,A
CB6F28
BIT 5,B
CB6828
BIT 5,C
CB6928
BIT 5,D
CB6A28
BIT 5,E
CB6B28
BIT 5,H
CB6C28
BIT 5,L
CB6D28
BIT 5,(HL)
CB6E212
BIT 5,(IX+d)
DDCBnn6E420
BIT 5,(IY+d)
FDCBnn6E420
BIT 6
BIT 6,A
CB7728
BIT 6,B
CB7028
BIT 6,C
CB7128
BIT 6,D
CB7228
BIT 6,E
CB7328
BIT 6,H
CB7428
BIT 6,L
CB7528
BIT 6,(HL)
CB76212
BIT 6,(IX+d)
DDCBnn76420
BIT 6,(IY+d)
FDCBnn76420
BIT 7
BIT 7,A
CB7F28
BIT 7,B
CB7828
BIT 7,C
CB7928
BIT 7,D
CB7A28
BIT 7,E
CB7B28
BIT 7,H
CB7C28
BIT 7,L
CB7D28
BIT 7,(HL)
CB7E212
BIT 7,(IX+d)
DDCBnn7E420
BIT 7,(IY+d)
FDCBnn7E420
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

6.2 - RES

Reset a specific bit
76543210
 
\(r_b \longleftarrow 0\)
RES b, r
11001011CB
10br
 
\((HL)_b \longleftarrow 0\)
RES b, (HL)
11001011CB
10b110
 
\((IX+d)_b \longleftarrow 0\)
RES b, (IX+d)
11011101DD
11001011CB
d
10b110
 
\((IY+d)_b \longleftarrow 0\)
RES b, (IY+d)
11111101FD
11001011CB
d
10b110
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

Flags Affected
None.
Opcode Matrix
Source
ABCDEHL(HL)(IX+d)(IY+d)
RES 0
RES 0,A
CB8728
RES 0,B
CB8028
RES 0,C
CB8128
RES 0,D
CB8228
RES 0,E
CB8328
RES 0,H
CB8428
RES 0,L
CB8528
RES 0,(HL)
CB86215
RES 0,(IX+d)
DDCBnn86423
RES 0,(IY+d)
FDCBnn86423
RES 1
RES 1,A
CB8F28
RES 1,B
CB8828
RES 1,C
CB8928
RES 1,D
CB8A28
RES 1,E
CB8B28
RES 1,H
CB8C28
RES 1,L
CB8D28
RES 1,(HL)
CB8E215
RES 1,(IX+d)
DDCBnn8E423
RES 1,(IY+d)
FDCBnn8E423
RES 2
RES 2,A
CB9728
RES 2,B
CB9028
RES 2,C
CB9128
RES 2,D
CB9228
RES 2,E
CB9328
RES 2,H
CB9428
RES 2,L
CB9528
RES 2,(HL)
CB96215
RES 2,(IX+d)
DDCBnn96423
RES 2,(IY+d)
FDCBnn96423
RES 3
RES 3,A
CB9F28
RES 3,B
CB9828
RES 3,C
CB9928
RES 3,D
CB9A28
RES 3,E
CB9B28
RES 3,H
CB9C28
RES 3,L
CB9D28
RES 3,(HL)
CB9E215
RES 3,(IX+d)
DDCBnn9E423
RES 3,(IY+d)
FDCBnn9E423
RES 4
RES 4,A
CBA728
RES 4,B
CBA028
RES 4,C
CBA128
RES 4,D
CBA228
RES 4,E
CBA328
RES 4,H
CBA428
RES 4,L
CBA528
RES 4,(HL)
CBA6215
RES 4,(IX+d)
DDCBnnA6423
RES 4,(IY+d)
FDCBnnA6423
RES 5
RES 5,A
CBAF28
RES 5,B
CBA828
RES 5,C
CBA928
RES 5,D
CBAA28
RES 5,E
CBAB28
RES 5,H
CBAC28
RES 5,L
CBAD28
RES 5,(HL)
CBAE215
RES 5,(IX+d)
DDCBnnAE423
RES 5,(IY+d)
FDCBnnAE423
RES 6
RES 6,A
CBB728
RES 6,B
CBB028
RES 6,C
CBB128
RES 6,D
CBB228
RES 6,E
CBB328
RES 6,H
CBB428
RES 6,L
CBB528
RES 6,(HL)
CBB6215
RES 6,(IX+d)
DDCBnnB6423
RES 6,(IY+d)
FDCBnnB6423
RES 7
RES 7,A
CBBF28
RES 7,B
CBB828
RES 7,C
CBB928
RES 7,D
CBBA28
RES 7,E
CBBB28
RES 7,H
CBBC28
RES 7,L
CBBD28
RES 7,(HL)
CBBE215
RES 7,(IX+d)
DDCBnnBE423
RES 7,(IY+d)
FDCBnnBE423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

6.3 - SET

Set a specific bit
76543210
 
\(r_b \longleftarrow 1\)
SET b, r
11001011CB
11br
 
\((HL)_b \longleftarrow 1\)
SET b, (HL)
11001011CB
11b110
 
\((IX+d)_b \longleftarrow 1\)
SET b, (IX+d)
11011101DD
11001011CB
d
11b110
 
\((IY+d)_b \longleftarrow 1\)
SET b, (IY+d)
11111101FD
11001011CB
d
11b110
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

Flags Affected
None.
Opcode Matrix
Source
ABCDEHL(HL)(IX+d)(IY+d)
SET 0
SET 0,A
CBC728
SET 0,B
CBC028
SET 0,C
CBC128
SET 0,D
CBC228
SET 0,E
CBC328
SET 0,H
CBC428
SET 0,L
CBC528
SET 0,(HL)
CBC6215
SET 0,(IX+d)
DDCBnnC6423
SET 0,(IY+d)
FDCBnnC6423
SET 1
SET 1,A
CBCF28
SET 1,B
CBC828
SET 1,C
CBC928
SET 1,D
CBCA28
SET 1,E
CBCB28
SET 1,H
CBCC28
SET 1,L
CBCD28
SET 1,(HL)
CBCE215
SET 1,(IX+d)
DDCBnnCE423
SET 1,(IY+d)
FDCBnnCE423
SET 2
SET 2,A
CBD728
SET 2,B
CBD028
SET 2,C
CBD128
SET 2,D
CBD228
SET 2,E
CBD328
SET 2,H
CBD428
SET 2,L
CBD528
SET 2,(HL)
CBD6215
SET 2,(IX+d)
DDCBnnD6423
SET 2,(IY+d)
FDCBnnD6423
SET 3
SET 3,A
CBDF28
SET 3,B
CBD828
SET 3,C
CBD928
SET 3,D
CBDA28
SET 3,E
CBDB28
SET 3,H
CBDC28
SET 3,L
CBDD28
SET 3,(HL)
CBDE215
SET 3,(IX+d)
DDCBnnDE423
SET 3,(IY+d)
FDCBnnDE423
SET 4
SET 4,A
CBE728
SET 4,B
CBE028
SET 4,C
CBE128
SET 4,D
CBE228
SET 4,E
CBE328
SET 4,H
CBE428
SET 4,L
CBE528
SET 4,(HL)
CBE6215
SET 4,(IX+d)
DDCBnnE6423
SET 4,(IY+d)
FDCBnnE6423
SET 5
SET 5,A
CBEF28
SET 5,B
CBE828
SET 5,C
CBE928
SET 5,D
CBEA28
SET 5,E
CBEB28
SET 5,H
CBEC28
SET 5,L
CBED28
SET 5,(HL)
CBEE215
SET 5,(IX+d)
DDCBnnEE423
SET 5,(IY+d)
FDCBnnEE423
SET 6
SET 6,A
CBF728
SET 6,B
CBF028
SET 6,C
CBF128
SET 6,D
CBF228
SET 6,E
CBF328
SET 6,H
CBF428
SET 6,L
CBF528
SET 6,(HL)
CBF6215
SET 6,(IX+d)
DDCBnnF6423
SET 6,(IY+d)
FDCBnnF6423
SET 7
SET 7,A
CBFF28
SET 7,B
CBF828
SET 7,C
CBF928
SET 7,D
CBFA28
SET 7,E
CBFB28
SET 7,H
CBFC28
SET 7,L
CBFD28
SET 7,(HL)
CBFE215
SET 7,(IX+d)
DDCBnnFE423
SET 7,(IY+d)
FDCBnnFE423
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

7 - Exchanges

Exchange registers

These instructions exchange values between registers.

76543210
 
\(AF \longleftrightarrow AF'\)
EX AF, AF'
0000100008
 
\(BC \longleftrightarrow BC', DE \longleftrightarrow DE', HL \longleftrightarrow HL'\)
EXX
11011001D9
 
\(DE \longleftrightarrow HL\)
EX DE, HL
11101011EB
 
\(H \longleftrightarrow (SP+1), L \longleftrightarrow (SP)\)
EX (SP), HL
11100011E3
 
\(IX_h \longleftrightarrow (SP+1), IX_l \longleftrightarrow (SP)\)
EX (SP), IX
11011101DD
11100011E3
 
\(IY_h \longleftrightarrow (SP+1), IY_l \longleftrightarrow (SP)\)
EX (SP), IY
11111101FD
11100011E3

EX AF, AF' (0x08) allows the programmer to switch between the two pairs of Accumulator flag registers.

EX DE, HL (0xEB) exchanges the values between those two registers.

EXX (0xD9) allows the programmer to switch BC, DE and HL and BC', DE' and HL' register pairs.

Internally these instructions toggles a flip-flop which determines which register or register set is the active one. This minimises how long the instruction takes as no data is transferred - just a single bit changes state.

EX (SP),HL exchanges HL with the last value pushed on the stack.

Flags Affected
None.
Opcode Matrix
AF'HLIXIYBC',DE',HL'
AF
EX AF, AF'
0814




DE

EX DE, HL
EB14



(SP)

EX (SP), HL
E3119
EX (SP), IX
DDE3223
EX (SP), IY
FDE3223

BC,DE,HL




EXX
D914
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register Memory

8 - Block Copy or Search of memory

Copy or search block of memory

8.1 - Block Copy

Copy block of memory

The Block copy instructions allow for data to be moved around in memory. The programmer needs to configure the 16 bit registers to define the properties of the move: HL is the source address to copy from; DE is the destination address to copy to; BC is the number of bytes to copy.

\(\begin{rcases} \begin{rcases} HL \longleftarrow HL+1 \\ DE \longleftarrow DE+1 \end{rcases} \text{ if } D = 0\\ \begin{rcases} HL \longleftarrow HL-1 \\DE \longleftarrow DE-1 \end{rcases} \text{ if } D=1 \\BC \longleftarrow BC-1 \end{rcases} \text{repeat while } \begin{cases} L=1\\BC \not = 0 \end{cases}\)

76543210
11101101ED
101LD000

D 0=Increment, 1=Decrement HL after each iteration.

L If set then if \( BC \not = 0 \) at the end if the instruction then \( PC \longleftarrow PC - 2 \) so that the instruction is repeated.
If BC=0 at start of a repeatable instruction then 65536 iterations will occur.

The LD* instructions then perform the equivalent of the following:

  1. Copy a byte of memory from (HL) to (DE)
  2. Decrement BC by one
  3. HL and DE are either incremented (for LDI/LDIR) or decremented (for LDD/LDDR) by one.
  4. The LDIR and LDDR instructions will loop back to step one if \( BC \not = 0 \)

Timing

For the non-repeating instructions, they take 16(4,4,3,5) T-States to execute.

For the repeating instructions, they take either 21(4,4,3,5,5) T-States when they loop and 16(4,4,3,5) T-States when terminating.

Also note, that for these instructions the timing is for each iteration, not for the entire run. So if LDIR is run with BC=4 then the number of T-States for the entire operation would take 79(21+21+21+16) T-States.

Flags Affected
Flags
---h-p/v--
hReset
p/vNon-repeating: Set if BC-1 != 0, otherwise reset
Repeating: N/A as BC=0 after instruction completes
Opcode Matrix
IncrementDecrement
Single Copy
LDI
EDA0216
LDD
EDA8216
Repeat Copy
LDIR
EDB0221
LDDR
EDB8221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

8.2 - Block Search of memory

Search block of memory

The Block compare instructions allow for data to be searched for in memory. The programmer needs to configure the following registers to define the properties of the search: HL is the source address to search from; BC is the number of bytes to search. A is set to the value to search for.

\(\begin{rcases} A-(HL) \\ HL \longleftarrow HL+1 \text{ if } D = 0\\ HL \longleftarrow HL-1 \text{ if } D=1 \\BC \longleftarrow BC-1 \end{rcases} \text{repeat while } \begin{cases} L=1\\A \not = (HL)\\BC \not = 0 \end{cases}\)

76543210
11101101ED
101LD001

D 0=Increment, 1=Decrement HL after each iteration.

L If set then if \( BC \not = 0 \) at the end if the instruction then \( PC \longleftarrow PC - 2 \) so that the instruction is repeated.
If BC=0 at start of a repeatable instruction then 65536 iterations will occur.

The CP* instructions compare memory against the Accumulator

  1. Calculate difference between A and content of memory in (HL) to set/clear Z flag
  2. Decrement BC by one
  3. HL is either incremented (for CPI/CPIR) or decremented (for CPD/CPDR) by one.
  4. The CPIR and CPDR instructions will loop back to step one if \( A-(HL) \not = 0 \And BC \not = 0 \)
    If the value was found them HL will be set to the byte after or before it depending on the direction being used.

Timing

For the non-repeating instructions, they take 16(4,4,3,5) T-States to execute.

For the repeating instructions, they take either 21(4,4,3,5,5) T-States when they loop and 16(4,4,3,5) T-States when terminating.

Also note, that for these instructions the timing is for each iteration, not for the entire run. So if LDIR is run with BC=4 then the number of T-States for the entire operation would take 79(21+21+21+16) T-States.

Flags Affected
Flags
sz-h-p/v--
sSet if result is negative
zSet if A = (HL)
hBorrow from bit 4, otherwise reset
p/vNon-repeating: Set if BC-1 != 0, otherwise reset
Repeating: N/A as BC=0 after instruction completes
Opcode Matrix
IncrementDecrement
Single Search
CPI
EDA1216
CPD
EDA9216
Repeat Search
CPIR
EDB1221
CPDR
EDB9221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Memory

9 - Input/Output

Input Output instructions

9.1 - IN A, (n)

Read from port and store in A

\(A \longleftarrow (n)\)

76543210
11011011DB
n

This instruction places n onto the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of the Accumulator also appear on the top half (A8…A15) of the address bus at this time. One byte from the selected port is placed on the data bus and written to the Accumulator (Register A).

Flags Affected
None.
Opcode Matrix
A
IN (n)
IN A,(n)
DBnn211
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

9.2 - IN r,(C)

Read from port in C and store in a specific register
76543210
 
\(r \longleftarrow (C)\)
IN r, (C)
11101101ED
01r000
 
\(F \longleftarrow (C)\)
IN F, (C)
11101101ED
0111000070
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

The contents of Register C are placed on the bottom half (A0…7) of the address bus to select the I/O device at one of 256 possible ports. The contents of Register B are placed on the top half (A8…A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to register r in the CPU.

There is an undocumented code where r=%110 which sets the flag register.

This is actually documented in Zilog's Z80 CPU User Manual, 2016 edition Page 296. For this reason it's included on this page and not in the Undocumented instruction section.

Flags Affected
Flags
sz-h-p/vn-
sset if input data is negative
zset if input data is 0
hreset
p/vset if parity is even, reset if odd
nreset
Opcode Matrix
ABCDEHLF
IN (C)
IN A,(C)
ED7B212
IN B,(C)
ED40212
IN C,(C)
ED48212
IN D,(C)
ED50212
IN E,(C)
ED58212
IN H,(C)
ED60212
IN L,(C)
ED68212
IN F,(C)
ED70212
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special Undocumented

9.3 - OUT (C), r

Write r to a port
76543210
 
\((C) \longleftarrow r\)
OUT (C), r
11101101ED
01r001
 
\((C) \longleftarrow F\)
OUT (C), F
11101101ED
0111000171
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

The contents of Register C are placed on the bottom half (A0…7) of the address bus to select the I/O device at one of 256 possible ports.

The contents of Register B are placed on the top half (A8…A15) of the address bus at this time.

Then the byte contained in r is placed on the data bus and written to the selected peripheral device.

There is an undocumented code where r=%110 which writes the flag register.

Unlike it's IN F, (C) counterpart, this instruction is completely undocumented, but it's here not in the undocumented section to be consistent.

Flags Affected
None.
Opcode Matrix
ABCDEHLF
OUT (C)
OUT (C),A
ED79212
OUT (C),B
ED41212
OUT (C),C
ED49212
OUT (C),D
ED51212
OUT (C),E
ED59212
OUT (C),H
ED61212
OUT (C),L
ED69212
OUT (C),F
ED71212
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special Undocumented

9.4 - OUT (n), A

Write A to a port

\((n) \longleftarrow A\)

76543210
11010011D3
n

This instruction places n onto the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.

The contents of the Accumulator also appear on the top half (A8…A15) of the address bus at this time.

Then the byte contained in the Accumulator is placed on the data bus and written to the selected peripheral device.

Flags Affected
None.
Opcode Matrix
A
OUT (n)
OUT (n),A
D3nn211
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

9.5 - Block read from port

\(\begin{rcases} (HL) \longleftarrow (C)\\HL \longleftarrow HL+1 \text{ if } D = 0\\HL \longleftarrow HL-1 \text{ if } D = 1\\B \longleftarrow B-1 \end{rcases} \text{repeat while } L=1 \And B \not = 0\)

76543210
11101101ED
101LD010

D 0=Increment, 1=Decrement HL after each iteration

L If set then if \(B \not = 0\) then \(PC \longleftarrow PC-2\) so that the instruction is repeated.

The contents of Register C are placed on the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.

Register B can be used as a byte counter, and its contents are placed on the top half (A8…15) of the address bus at this time.

Then one byte from the selected port is placed on the data bus and written to the CPU.

The contents of the HL register pair are then placed on the address bus and the input byte is written to the corresponding location of memory.

Finally, the byte counter is decremented and register pair HL is incremented.

Flags Affected
Flags
-z----n-
zset if B = 0, always true for repeat operations
nset
Opcode Matrix
IncrementDecrement
Single
INI
EDA2216
IND
EDAA216
Repeat
INIR
EDB2221
INDR
EDBA221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

9.6 - Block write to port

\(\begin{rcases} (C) \longleftarrow (HL)\\HL \longleftarrow HL+1 \text{ if } D = 0\\HL \longleftarrow HL-1 \text{ if } D = 1\\B \longleftarrow B-1 \end{rcases} \text{repeat while } L=1 \And B \not = 0\)

76543210
11101101ED
101LD011

D 0=Increment, 1=Decrement HL after each iteration

L If set then if \(B \not = 0\) then \(PC \longleftarrow PC-2\) so that the instruction is repeated.

The contents of Register C are placed on the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.

Register B can be used as a byte counter, and its contents are placed on the top half (A8…15) of the address bus at this time.

Then one byte from the address pointed to by HL is placed on the data bus and written to the port.

Finally, the byte counter is decremented and register pair HL is incremented.

Flags Affected
Flags
-z----n-
zset if B = 0, always true for repeat operations
nset
Opcode Matrix
IncrementDecrement
Single
OUTI
EDA3216
OUTD
EDAB216
Repeat
OUTIR
EDB3221
OUTDR
EDBB221
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

10 - Miscellaneous Instructions

Miscellaneous instructions

10.1 - NOP No Operation

76543210
0000000000
Opcode Matrix
NOP
OP
NOP
0014
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

10.2 - CPL Invert Accumulator

\(A \longleftarrow \overline{A}\)

76543210
001011112F
Flags Affected
Flags
---h--n-
hset
nset
Opcode Matrix
CPL
OP
CPL
2F14
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

10.3 - NEG Negate Accumulator (two's compliment)

\(A \longleftarrow 0 - A\)

76543210
11101101ED
0100010044
Flags Affected
Flags
sz-h-p/vnc
sset if result is negative
zset if result is 0
hset if borrow from bit 4
p/vset if Accumulator was 0x80 before operation
nset
cset if Accumulator was not 0x00 before operation
Opcode Matrix
NEG
OP
NEG
ED4424
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

10.4 - HALT the cpu

76543210
0111011076
Opcode Matrix
HALT
OP
HALT
7614
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Special

10.5 - CCF Compliment Carry Flag

Invert Carry Flag

\(CY \longleftarrow \overline{CY}\)

76543210
001111113F
Flags Affected
Flags
---h---c
hprevious carry is copied
cset if C was 0, reset if C was 1
Opcode Matrix
CCF
OP
CCF
3F14
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

10.6 - SCF Set Carry Flag

Set Carry Flag

\(CY \longleftarrow 1\)

76543210
0011011137
Flags Affected
Flags
---h--nc
hreset
nreset
cset
Opcode Matrix
CPLNEGCCFSCF
OP
CPL
2F14
NEG
ED4424
CCF
3F14
SCF
3714
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

10.7 - DI EI Interrupt enable

Enable/Disable interrupts
76543210
 
\(IFF \longleftarrow 0\)
DI
11110011
 
\(IFF \longleftarrow 1\)
EI
11111011
Opcode Matrix
EIDI
OP
EI
FB14
DI
F314
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Interrupt

10.8 - IM Interrupt Mode

Select interrupt mode
76543210
11101101ED
010QQ110

Note: Only modes 0, 1 and 2 are valid for IM n.

Opcode Matrix
IM0IM1IM2
OP
IM0
ED4628
IM1
ED5628
IM2
ED5E28
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Interrupt

10.9 - DAA

Adjust accumulator for BCD addition and subtraction operations

\(@\)

76543210
0010011127
Flags Affected
Flags
-z-h-p/v-c
zSet if Accumulator is 0
hVaries
p/vSet if Accumulator parity is even, reset if odd
cVaries
Opcode Matrix
DAA
OP
DAA
2714
Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count
 Register

11 - Undocumented Instructions

Undocumented instructions - use with care

Like most early microprocessors, the Z80 has it's own set of undocumented instructions.

Most of these either do something that's not useful, or they do something that would at first seem to be odd in why they were implemented in the first place.

In most instances, they exist due to how the processor is implemented in silicon. Where an instruction is decoded, there are free bits so if something tried to use that code then the processor would just do as it's told as it wouldn't know otherwise.

Be aware, these usually work on a physical chip due to it requiring the actual instruction decoding to provide these instructions.

They will most likely not work in an emulator as they would perform the decoding in software using lookup tables, so wouldn't implement anything that's not documented.

These may or may not work on actual chips. For example, on the 6502 there were plenty of undocumented instructions that were replaced in the 65C02 with NOP instructions.

These are provided here for reference only.

Overview

Most of the undocumented instructions fall under some simple rules:

CB

Only codes 0xCB30…0xCB37 are undocumented but implement a Shift Logical Left instruction where bit 0 is set post shift.

DDCB & FDCB

For opcodes with the 0xDDCB and 0xFDCB prefixes the instructions store the result in one of the 8-bit registers based on the lower 3 bits of the opcode: B=000, C=001, D=010, E=011, H=100, L=101 and A=111.

The officially documented codes all have 110 as the lower 3 bits and do not store the result in any register.

All of these instructions with the 0xDDCB prefix operate against the IX register (IY for 0xFDBC).

The only exception to this rule is opcodes 0x40…0x7F which are the bit text operations. As these only test the memory location they do not create a result so all the undocumented versions are identical to the official instructions.

DD & FD

Officially the 0xDD and 0xFD prefixes cause any instruction that references (HL) to instead work against the IX & IY registers with a displacement, 0xDD for IX and 0xFD for IY.

The undocumented instructions allows for instructions that refer to just H or L can also be used to access the upper or lower 8-bit components of IX and IY themselves.

ED

There are a few undocumented instructions with this prefix, but they simply emulate existing instructions.

The exception to this are the IN F, (C) and OUT (C), F instructions which are described below.

When is undocumented actually documented?

One oddity is the undocumented IN F,(C)0xED70 instruction which performs an IN from an I/O port but stores the result into the Flags register. This instruction is actually documented in Zilogs own documentation (2016 PDF). For this reason, that instruction is listed on the IN r, (C) page and not in this section.

It's OUT (C), F0xED71 equivalent is listed under OUT (C), r for consistency, even though that instruction is completely undocumented.

11.1 - Dual Shift Operations

Undocumented instructions that perform two actions at the same time

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official RLC (IX+nn)0xDDCBnn06 instruction operates on a specific memory address, however the undocumented RLC B,(IX+nn)0xDDCBnn00 instruction does the same thing but then copies the result into the B register.

11.1.1 - RL Rotate bits left with Carry and store in register

Undocumented Rotate bits left with carry and store in register

This instruction performs an RL (IX+dd) or RL (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RL instruction

76543210
 
RL r,(IX+d)
11011101DD
11001011CB
d
00010r
 
RL r,(IY+d)
11111101FD
11001011CB
d
00010r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RL A,(IX+d)
DDCBnn17
RL B,(IX+d)
DDCBnn10
RL C,(IX+d)
DDCBnn11
RL D,(IX+d)
DDCBnn12
RL E,(IX+d)
DDCBnn13
RL H,(IX+d)
DDCBnn14
RL L,(IX+d)
DDCBnn15
(IY+d)
RL A,(IY+d)
FDCBnn17
RL B,(IY+d)
FDCBnn10
RL C,(IY+d)
FDCBnn11
RL D,(IY+d)
FDCBnn12
RL E,(IY+d)
FDCBnn13
RL H,(IY+d)
FDCBnn14
RL L,(IY+d)
FDCBnn15
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.1.2 - RLC Rotate bits left with Carry and store in register

Undocumented Rotate bits left with carry and store in register

This instruction performs an RLC (IX+dd) or RLC (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RLC instruction

76543210
 
RLC r,(IX+d)
11011101DD
11001011CB
d
00000r
 
RLC r,(IY+d)
11111101FD
11001011CB
d
00000r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RLC A,(IX+d)
DDCBnn07
RLC B,(IX+d)
DDCBnn00
RLC C,(IX+d)
DDCBnn01
RLC D,(IX+d)
DDCBnn02
RLC E,(IX+d)
DDCBnn03
RLC H,(IX+d)
DDCBnn04
RLC L,(IX+d)
DDCBnn05
(IY+d)
RLC A,(IY+d)
FDCBnn07
RLC B,(IY+d)
FDCBnn00
RLC C,(IY+d)
FDCBnn01
RLC D,(IY+d)
FDCBnn02
RLC E,(IY+d)
FDCBnn03
RLC H,(IY+d)
FDCBnn04
RLC L,(IY+d)
FDCBnn05
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.1.3 - RR Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an RR (IX+dd) or RR (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RR instruction

76543210
 
RR r,(IX+d)
11011101DD
11001011CB
d
00011r
 
RR r,(IY+d)
11111101FD
11001011CB
d
00011r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RR A,(IX+d)
DDCBnn1F
RR B,(IX+d)
DDCBnn18
RR C,(IX+d)
DDCBnn19
RR D,(IX+d)
DDCBnn1A
RR E,(IX+d)
DDCBnn1B
RR H,(IX+d)
DDCBnn1C
RR L,(IX+d)
DDCBnn1D
(IY+d)
RR A,(IY+d)
FDCBnn1F
RR B,(IY+d)
FDCBnn18
RR C,(IY+d)
FDCBnn19
RR D,(IY+d)
FDCBnn1A
RR E,(IY+d)
FDCBnn1B
RR H,(IY+d)
FDCBnn1C
RR L,(IY+d)
FDCBnn1D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.1.4 - RRC Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an RRC (IX+dd) or RRC (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the RRC instruction

76543210
 
RRC r,(IX+d)
11011101DD
11001011CB
d
00001r
 
RRC r,(IY+d)
11111101FD
11001011CB
d
00001r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
RRC A,(IX+d)
DDCBnn0F
RRC B,(IX+d)
DDCBnn08
RRC C,(IX+d)
DDCBnn09
RRC D,(IX+d)
DDCBnn0A
RRC E,(IX+d)
DDCBnn0B
RRC H,(IX+d)
DDCBnn0C
RRC L,(IX+d)
DDCBnn0D
(IY+d)
RRC A,(IY+d)
FDCBnn0F
RRC B,(IY+d)
FDCBnn08
RRC C,(IY+d)
FDCBnn09
RRC D,(IY+d)
FDCBnn0A
RRC E,(IY+d)
FDCBnn0B
RRC H,(IY+d)
FDCBnn0C
RRC L,(IY+d)
FDCBnn0D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.1.5 - SLA Shift bits left with Carry and store in register

Undocumented Shift bits left with carry and store in register

This instruction performs an SLA (IX+dd) or SLA (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the SLA instruction

76543210
 
SLA r,(IX+d)
11011101DD
11001011CB
d
00100r
 
SLA r,(IY+d)
11111101FD
11001011CB
d
00100r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SLA A,(IX+d)
DDCBnn27
SLA B,(IX+d)
DDCBnn20
SLA C,(IX+d)
DDCBnn21
SLA D,(IX+d)
DDCBnn22
SLA E,(IX+d)
DDCBnn23
SLA H,(IX+d)
DDCBnn24
SLA L,(IX+d)
DDCBnn25
(IY+d)
SLA A,(IY+d)
FDCBnn27
SLA B,(IY+d)
FDCBnn20
SLA C,(IY+d)
FDCBnn21
SLA D,(IY+d)
FDCBnn22
SLA E,(IY+d)
FDCBnn23
SLA H,(IY+d)
FDCBnn24
SLA L,(IY+d)
FDCBnn25
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.1.6 - SLL Shift left Logical and store in register

Undocumented Shift left logical and store in register

This instruction performs an SLL (IX+dd) or SLL (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Note: This is an undocumented extension to an undocumented instruction.

Visualisation of the SLL instruction

76543210
 
SLL r,(IX+d)
11011101DD
11001011CB
d
00110r
 
SLL r,(IY+d)
11111101FD
11001011CB
d
00110r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SLL A,(IX+d)
DDCBnn37
SLL B,(IX+d)
DDCBnn30
SLL C,(IX+d)
DDCBnn31
SLL D,(IX+d)
DDCBnn32
SLL E,(IX+d)
DDCBnn33
SLL H,(IX+d)
DDCBnn34
SLL L,(IX+d)
DDCBnn35
(IY+d)
SLL A,(IY+d)
FDCBnn37
SLL B,(IY+d)
FDCBnn30
SLL C,(IY+d)
FDCBnn31
SLL D,(IY+d)
FDCBnn32
SLL E,(IY+d)
FDCBnn33
SLL H,(IY+d)
FDCBnn34
SLL L,(IY+d)
FDCBnn35
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.1.7 - SRA Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an SRA (IX+dd) or SRA (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the SRA instruction

76543210
 
SRA r,(IX+d)
11011101DD
11001011CB
d
00101r
 
SRA r,(IY+d)
11111101FD
11001011CB
d
00101r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SRA A,(IX+d)
DDCBnn2F
SRA B,(IX+d)
DDCBnn28
SRA C,(IX+d)
DDCBnn29
SRA D,(IX+d)
DDCBnn2A
SRA E,(IX+d)
DDCBnn2B
SRA H,(IX+d)
DDCBnn2C
SRA L,(IX+d)
DDCBnn2D
(IY+d)
SRA A,(IY+d)
FDCBnn2F
SRA B,(IY+d)
FDCBnn28
SRA C,(IY+d)
FDCBnn29
SRA D,(IY+d)
FDCBnn2A
SRA E,(IY+d)
FDCBnn2B
SRA H,(IY+d)
FDCBnn2C
SRA L,(IY+d)
FDCBnn2D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.1.8 - SRL Rotate bits right with Carry and store in register

Undocumented Rotate bits right with carry and store in register

This instruction performs an SRL (IX+dd) or SRL (IX+dd) operation but then also stores the result in a register as well as in the memory location.

Visualisation of the SRL instruction

76543210
 
SRL r,(IX+d)
11011101DD
11001011CB
d
00111r
 
SRL r,(IY+d)
11111101FD
11001011CB
d
00111r
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111

Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.

Opcode Matrix
ABCDEHL
(IX+d)
SRL A,(IX+d)
DDCBnn3F
SRL B,(IX+d)
DDCBnn38
SRL C,(IX+d)
DDCBnn39
SRL D,(IX+d)
DDCBnn3A
SRL E,(IX+d)
DDCBnn3B
SRL H,(IX+d)
DDCBnn3C
SRL L,(IX+d)
DDCBnn3D
(IY+d)
SRL A,(IY+d)
FDCBnn3F
SRL B,(IY+d)
FDCBnn38
SRL C,(IY+d)
FDCBnn39
SRL D,(IY+d)
FDCBnn3A
SRL E,(IY+d)
FDCBnn3B
SRL H,(IY+d)
FDCBnn3C
SRL L,(IY+d)
FDCBnn3D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.2 - IX and IY registers

Undocumented instructions for IX and IY registers

If an opcode works with the Registers HL, H or L then if that opcode is prefixed by 0xDD then it will also work on the appropriate IX, IXh or IXl registers, with some exceptions.

The 0xFD prefix would also work but for the IY, IYh or IYl registers

The exceptions are instructions like LD H,IXh or LD L,IYh where it isn't clear from the opcode which register the 0xFD or 0xDD prefix should operate against.

11.2.1 - LD IX undocumented instructions

Undocumented instructions for LD IX
Opcode Matrix
ABCDEnIXhIXl
A






LD A,IXh
DD7C
LD A,IXl
DD7D
B






LD B,IXh
DD44
LD B,IXl
DD45
C






LD C,IXh
DD4C
LD C,IXl
DD4D
D






LD D,IXh
DD54
LD D,IXl
DD55
E






LD E,IXh
DD5C
LD E,IXl
DD5D
IXh
LD IXh,A
DD67
LD IXh,B
DD60
LD IXh,C
DD61
LD IXh,D
DD62
LD IXh,E
DD63
LD IXh,n
DD26nn
LD IXh,IHh
DD64
LD IXh,IHl
DD65
IXl
LD IXl,A
DD6F
LD IXl,B
DD68
LD IXl,C
DD69
LD IXl,D
DD6A
LD IXl,E
DD6B
LD IXl,n
DD2Enn
LD IXl,IHh
DD6C
LD IXl,IHl
DD6D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.2.2 - LD IY undocumented instructions

Undocumented instructions for LD IY
Opcode Matrix
ABCDEnIYhIYl
A






LD A,IYh
FD7C
LD A,IYl
FD7D
B






LD B,IYh
FD44
LD B,IYl
FD45
C






LD C,IYh
FD4C
LD C,IYl
FD4D
D






LD D,IYh
FD54
LD D,IYl
FD55
E






LD E,IYh
FD5C
LD E,IYl
FD5D
IYh
LD IYh,A
FD67
LD IYh,B
FD60
LD IYh,C
FD61
LD IYh,D
FD62
LD IYh,E
FD63
LD IYh,n
FD26nn
LD IYh,IHh
FD64
LD IYh,IHl
FD65
IYl
LD IYl,A
FD6F
LD IYl,B
FD68
LD IYl,C
FD69
LD IYl,D
FD6A
LD IYl,E
FD6B
LD IYl,n
FD2Enn
LD IYl,IHh
FD6C
LD IYl,IHl
FD6D
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.2.3 - Undocumented Math instructions with the IX register

Undocumented math instructions for IX register
Opcode Matrix
INCDECADD AADC ASUBSBC AANDXORORCP
IXh
INC IXh
DD24
DEC IXh
DD25
ADD A,IXh
DD84
ADC A,IXh
DD8C
SUB IXh
DD94
SBC A,IXh
DD9C
AND IXh
DDA4
XOR IXh
DDAC
OR IXh
DDB4
CP IXh
DDBC
IXl
INC IXl
DD2C
DEC IXl
DD2D
ADD A,IXl
DD85
ADC A,IXl
DD8D
SUB IXl
DD95
SBC A,IXl
DD9D
AND IXl
DDA5
XOR IXl
DDAD
OR IXl
DDB5
CP IXl
DDBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.2.4 - Undocumented Math instructions with the IY register

Undocumented math instructions for IY register
Opcode Matrix
INCDECADD AADC ASUBSBC AANDXORORCP
IYh
INC IYh
FD24
DEC IYh
FD25
ADD A,IYh
FD84
ADC A,IYh
FD8C
SUB IYh
FD94
SBC A,IYh
FD9C
AND IYh
FDA4
XOR IYh
FDAC
OR IYh
FDB4
CP IYh
FDBC
IYl
INC IYl
FD2C
DEC IYl
FD2D
ADD A,IYl
FD85
ADC A,IYl
FD8D
SUB IYl
FD95
SBC A,IYl
FD9D
AND IYl
FDA5
XOR IYl
FDAD
OR IYl
FDB5
CP IYl
FDBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.3 - SLL Shift Left Logical

Undocumented instruction to perform a logical left shift

The block CB30…CB37 is missing from the official list.

These instructions, usually denoted by the mnemonic SLL, Shift Left Logical, shift left the operand and make bit 0 always one.

These instructions are quite commonly used. For example, Bounder and Enduro Racer use them.

Some documents list this as SL1 instead of SLL due to it setting bit 0.

Visualisation of the SLL instruction
76543210
 
SLL r
11001011CB
00000r
 
SLL (HL)
11001011CB
0000011006
 
SLL (IX+d)
11011101DD
11001011CB
d
0000011006
 
SLL (IY+d)
11111101FD
11001011CB
d
0000011006
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Opcode Matrix
ABCDEHL(HL)(IX+dd)(IY+dd)
SLL
SLL A
CB37
SLL B
CB30
SLL C
CB31
SLL D
CB32
SLL E
CB33
SLL H
CB34
SLL L
CB35
SLL (HL)
CB36
SLL (IX+dd)
DDCBnn36
SLL (IY+dd)
FDCBnn36
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.4 - Test bit in (IX+d)

Undocumented BIT n,(IX+d)

Similar to the RES and SET instructions, there are undocumented instructions for BIT. Unlike the other, as BIT only tests a bit and does not change anything, these opcodes have the same behaviour to the officially documented BIT instruction.

76543210
 
\(Z \longleftarrow \overline{(IX+d)_b}\)
BIT b, (IX+d)
11011101DD
11001011CB
d
01br
 
\(Z \longleftarrow \overline{(IY+d)_b}\)
BIT b, (IY+d)
11111101FD
11001011CB
d
01br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

r=%110 does exist, it is the official, documented operation.

11.5 - RES Reset bit in (IX+d) and copy into register r

Undocumented Reset bit in (IX+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official RES 0,(IX+nn) instruction resets bit 0 on a specific memory address, however the undocumented RES B,0,(IX+nn)0xDDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IX+d)_b \longleftarrow 0 \\ r \longleftarrow (IX+d)\)

76543210
11011101DD
11001011CB
d
10br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
RES A,0,(IX+nn)
DDCBnn87
RES A,1,(IX+nn)
DDCBnn8F
RES A,2,(IX+nn)
DDCBnn97
RES A,3,(IX+nn)
DDCBnn9F
RES A,4,(IX+nn)
DDCBnnA7
RES A,5,(IX+nn)
DDCBnnAF
RES A,6,(IX+nn)
DDCBnnB7
RES A,7,(IX+nn)
DDCBnnBF
B
RES B,0,(IX+nn)
DDCBnn80
RES B,1,(IX+nn)
DDCBnn88
RES B,2,(IX+nn)
DDCBnn90
RES B,3,(IX+nn)
DDCBnn98
RES B,4,(IX+nn)
DDCBnnA0
RES B,5,(IX+nn)
DDCBnnA8
RES B,6,(IX+nn)
DDCBnnB0
RES B,7,(IX+nn)
DDCBnnB8
C
RES C,0,(IX+nn)
DDCBnn81
RES C,1,(IX+nn)
DDCBnn89
RES C,2,(IX+nn)
DDCBnn91
RES C,3,(IX+nn)
DDCBnn99
RES C,4,(IX+nn)
DDCBnnA1
RES C,5,(IX+nn)
DDCBnnA9
RES C,6,(IX+nn)
DDCBnnB1
RES C,7,(IX+nn)
DDCBnnB9
D
RES D,0,(IX+nn)
DDCBnn82
RES D,1,(IX+nn)
DDCBnn8A
RES D,2,(IX+nn)
DDCBnn92
RES D,3,(IX+nn)
DDCBnn9A
RES D,4,(IX+nn)
DDCBnnA2
RES D,5,(IX+nn)
DDCBnnAA
RES D,6,(IX+nn)
DDCBnnB2
RES D,7,(IX+nn)
DDCBnnBA
E
RES E,0,(IX+nn)
DDCBnn83
RES E,1,(IX+nn)
DDCBnn8B
RES E,2,(IX+nn)
DDCBnn93
RES E,3,(IX+nn)
DDCBnn9B
RES E,4,(IX+nn)
DDCBnnA3
RES E,5,(IX+nn)
DDCBnnAB
RES E,6,(IX+nn)
DDCBnnB3
RES E,7,(IX+nn)
DDCBnnBB
H
RES H,0,(IX+nn)
DDCBnn84
RES H,1,(IX+nn)
DDCBnn8C
RES H,2,(IX+nn)
DDCBnn94
RES H,3,(IX+nn)
DDCBnn9C
RES H,4,(IX+nn)
DDCBnnA4
RES H,5,(IX+nn)
DDCBnnAC
RES H,6,(IX+nn)
DDCBnnB4
RES H,7,(IX+nn)
DDCBnnBC
L
RES L,0,(IX+nn)
DDCBnn85
RES L,1,(IX+nn)
DDCBnn8D
RES L,2,(IX+nn)
DDCBnn95
RES L,3,(IX+nn)
DDCBnn9D
RES L,4,(IX+nn)
DDCBnnA5
RES L,5,(IX+nn)
DDCBnnAD
RES L,6,(IX+nn)
DDCBnnB5
RES L,7,(IX+nn)
DDCBnnBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.6 - RES Reset bit in (IY+d) and copy into register r

Undocumented Reset bit in (IY+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official RES 0,(IY+nn) instruction resets bit 0 on a specific memory address, however the undocumented RES B,0,(IY+nn)0xFDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IY+d)_b \longleftarrow 0 \\ r \longleftarrow (IY+d)\)

76543210
11111101FD
11001011CB
d
10br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
RES A,0,(IY+nn)
FDCBnn87
RES A,1,(IY+nn)
FDCBnn8F
RES A,2,(IY+nn)
FDCBnn97
RES A,3,(IY+nn)
FDCBnn9F
RES A,4,(IY+nn)
FDCBnnA7
RES A,5,(IY+nn)
FDCBnnAF
RES A,6,(IY+nn)
FDCBnnB7
RES A,7,(IY+nn)
FDCBnnBF
B
RES B,0,(IY+nn)
FDCBnn80
RES B,1,(IY+nn)
FDCBnn88
RES B,2,(IY+nn)
FDCBnn90
RES B,3,(IY+nn)
FDCBnn98
RES B,4,(IY+nn)
FDCBnnA0
RES B,5,(IY+nn)
FDCBnnA8
RES B,6,(IY+nn)
FDCBnnB0
RES B,7,(IY+nn)
FDCBnnB8
C
RES C,0,(IY+nn)
FDCBnn81
RES C,1,(IY+nn)
FDCBnn89
RES C,2,(IY+nn)
FDCBnn91
RES C,3,(IY+nn)
FDCBnn99
RES C,4,(IY+nn)
FDCBnnA1
RES C,5,(IY+nn)
FDCBnnA9
RES C,6,(IY+nn)
FDCBnnB1
RES C,7,(IY+nn)
FDCBnnB9
D
RES D,0,(IY+nn)
FDCBnn82
RES D,1,(IY+nn)
FDCBnn8A
RES D,2,(IY+nn)
FDCBnn92
RES D,3,(IY+nn)
FDCBnn9A
RES D,4,(IY+nn)
FDCBnnA2
RES D,5,(IY+nn)
FDCBnnAA
RES D,6,(IY+nn)
FDCBnnB2
RES D,7,(IY+nn)
FDCBnnBA
E
RES E,0,(IY+nn)
FDCBnn83
RES E,1,(IY+nn)
FDCBnn8B
RES E,2,(IY+nn)
FDCBnn93
RES E,3,(IY+nn)
FDCBnn9B
RES E,4,(IY+nn)
FDCBnnA3
RES E,5,(IY+nn)
FDCBnnAB
RES E,6,(IY+nn)
FDCBnnB3
RES E,7,(IY+nn)
FDCBnnBB
H
RES H,0,(IY+nn)
FDCBnn84
RES H,1,(IY+nn)
FDCBnn8C
RES H,2,(IY+nn)
FDCBnn94
RES H,3,(IY+nn)
FDCBnn9C
RES H,4,(IY+nn)
FDCBnnA4
RES H,5,(IY+nn)
FDCBnnAC
RES H,6,(IY+nn)
FDCBnnB4
RES H,7,(IY+nn)
FDCBnnBC
L
RES L,0,(IY+nn)
FDCBnn85
RES L,1,(IY+nn)
FDCBnn8D
RES L,2,(IY+nn)
FDCBnn95
RES L,3,(IY+nn)
FDCBnn9D
RES L,4,(IY+nn)
FDCBnnA5
RES L,5,(IY+nn)
FDCBnnAD
RES L,6,(IY+nn)
FDCBnnB5
RES L,7,(IY+nn)
FDCBnnBD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.7 - SET bit in (IX+d) and copy into register r

Undocumented SET bit in (IX+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official SET 0,(IX+nn) instruction sets bit 0 on a specific memory address, however the undocumented SET B,0,(IX+nn)0xDDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IX+d)_b \longleftarrow 0 \\ r \longleftarrow (IX+d)\)

76543210
11111101DD
11001011CB
d
11br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
SET A,0,(IX+nn)
DDCBnnC7
SET A,1,(IX+nn)
DDCBnnCF
SET A,2,(IX+nn)
DDCBnnD7
SET A,3,(IX+nn)
DDCBnnDF
SET A,4,(IX+nn)
DDCBnnE7
SET A,5,(IX+nn)
DDCBnnEF
SET A,6,(IX+nn)
DDCBnnF7
SET A,7,(IX+nn)
DDCBnnFF
B
SET B,0,(IX+nn)
DDCBnnC0
SET B,1,(IX+nn)
DDCBnnC8
SET B,2,(IX+nn)
DDCBnnD0
SET B,3,(IX+nn)
DDCBnnD8
SET B,4,(IX+nn)
DDCBnnE0
SET B,5,(IX+nn)
DDCBnnE8
SET B,6,(IX+nn)
DDCBnnF0
SET B,7,(IX+nn)
DDCBnnF8
C
SET C,0,(IX+nn)
DDCBnnC1
SET C,1,(IX+nn)
DDCBnnC9
SET C,2,(IX+nn)
DDCBnnD1
SET C,3,(IX+nn)
DDCBnnD9
SET C,4,(IX+nn)
DDCBnnE1
SET C,5,(IX+nn)
DDCBnnE9
SET C,6,(IX+nn)
DDCBnnF1
SET C,7,(IX+nn)
DDCBnnF9
D
SET D,0,(IX+nn)
DDCBnnC2
SET D,1,(IX+nn)
DDCBnnCA
SET D,2,(IX+nn)
DDCBnnD2
SET D,3,(IX+nn)
DDCBnnDA
SET D,4,(IX+nn)
DDCBnnE2
SET D,5,(IX+nn)
DDCBnnEA
SET D,6,(IX+nn)
DDCBnnF2
SET D,7,(IX+nn)
DDCBnnFA
E
SET E,0,(IX+nn)
DDCBnnC3
SET E,1,(IX+nn)
DDCBnnCB
SET E,2,(IX+nn)
DDCBnnD3
SET E,3,(IX+nn)
DDCBnnDB
SET E,4,(IX+nn)
DDCBnnE3
SET E,5,(IX+nn)
DDCBnnEB
SET E,6,(IX+nn)
DDCBnnF3
SET E,7,(IX+nn)
DDCBnnFB
H
SET H,0,(IX+nn)
DDCBnnC4
SET H,1,(IX+nn)
DDCBnnCC
SET H,2,(IX+nn)
DDCBnnD4
SET H,3,(IX+nn)
DDCBnnDC
SET H,4,(IX+nn)
DDCBnnE4
SET H,5,(IX+nn)
DDCBnnEC
SET H,6,(IX+nn)
DDCBnnF4
SET H,7,(IX+nn)
DDCBnnFC
L
SET L,0,(IX+nn)
DDCBnnC5
SET L,1,(IX+nn)
DDCBnnCD
SET L,2,(IX+nn)
DDCBnnD5
SET L,3,(IX+nn)
DDCBnnDD
SET L,4,(IX+nn)
DDCBnnE5
SET L,5,(IX+nn)
DDCBnnED
SET L,6,(IX+nn)
DDCBnnF5
SET L,7,(IX+nn)
DDCBnnFD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented

11.8 - SET bit in (IY+d) and copy into register r

Undocumented SET bit in (IY+d) and copy into register r

There are a few undocumented instructions that performs an action and then copies the result into a register.

For example the official SET 0,(IY+nn) instruction sets bit 0 on a specific memory address, however the undocumented SET B,0,(IY+nn)0xFDCBnn00 instruction does the same thing but then copies the result into the B register.

\((IY+d)_b \longleftarrow 0 \\ r \longleftarrow (IY+d)\)

76543210
11111101FD
11001011CB
d
11br
Registers
Registerr
B000
C001
D010
E011
H100
L101
A111
Bits
Valueb
0000
1001
2010
3011
4100
5101
6110
7111

Z is set if the specified bit in the source is 0, otherwise it is cleared.

The result is stored both in memory and the specified register.

r=%110 does exist, it is the official documented operation with no auto-copy to a register.

Opcode Matrix
BIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7
A
SET A,0,(IY+nn)
FDCBnnC7
SET A,1,(IY+nn)
FDCBnnCF
SET A,2,(IY+nn)
FDCBnnD7
SET A,3,(IY+nn)
FDCBnnDF
SET A,4,(IY+nn)
FDCBnnE7
SET A,5,(IY+nn)
FDCBnnEF
SET A,6,(IY+nn)
FDCBnnF7
SET A,7,(IY+nn)
FDCBnnFF
B
SET B,0,(IY+nn)
FDCBnnC0
SET B,1,(IY+nn)
FDCBnnC8
SET B,2,(IY+nn)
FDCBnnD0
SET B,3,(IY+nn)
FDCBnnD8
SET B,4,(IY+nn)
FDCBnnE0
SET B,5,(IY+nn)
FDCBnnE8
SET B,6,(IY+nn)
FDCBnnF0
SET B,7,(IY+nn)
FDCBnnF8
C
SET C,0,(IY+nn)
FDCBnnC1
SET C,1,(IY+nn)
FDCBnnC9
SET C,2,(IY+nn)
FDCBnnD1
SET C,3,(IY+nn)
FDCBnnD9
SET C,4,(IY+nn)
FDCBnnE1
SET C,5,(IY+nn)
FDCBnnE9
SET C,6,(IY+nn)
FDCBnnF1
SET C,7,(IY+nn)
FDCBnnF9
D
SET D,0,(IY+nn)
FDCBnnC2
SET D,1,(IY+nn)
FDCBnnCA
SET D,2,(IY+nn)
FDCBnnD2
SET D,3,(IY+nn)
FDCBnnDA
SET D,4,(IY+nn)
FDCBnnE2
SET D,5,(IY+nn)
FDCBnnEA
SET D,6,(IY+nn)
FDCBnnF2
SET D,7,(IY+nn)
FDCBnnFA
E
SET E,0,(IY+nn)
FDCBnnC3
SET E,1,(IY+nn)
FDCBnnCB
SET E,2,(IY+nn)
FDCBnnD3
SET E,3,(IY+nn)
FDCBnnDB
SET E,4,(IY+nn)
FDCBnnE3
SET E,5,(IY+nn)
FDCBnnEB
SET E,6,(IY+nn)
FDCBnnF3
SET E,7,(IY+nn)
FDCBnnFB
H
SET H,0,(IY+nn)
FDCBnnC4
SET H,1,(IY+nn)
FDCBnnCC
SET H,2,(IY+nn)
FDCBnnD4
SET H,3,(IY+nn)
FDCBnnDC
SET H,4,(IY+nn)
FDCBnnE4
SET H,5,(IY+nn)
FDCBnnEC
SET H,6,(IY+nn)
FDCBnnF4
SET H,7,(IY+nn)
FDCBnnFC
L
SET L,0,(IY+nn)
FDCBnnC5
SET L,1,(IY+nn)
FDCBnnCD
SET L,2,(IY+nn)
FDCBnnD5
SET L,3,(IY+nn)
FDCBnnDD
SET L,4,(IY+nn)
FDCBnnE5
SET L,5,(IY+nn)
FDCBnnED
SET L,6,(IY+nn)
FDCBnnF5
SET L,7,(IY+nn)
FDCBnnFD
Opcode Matrix Legend
Instruction Opcode hex
 Undocumented