1 - Jump absolute

7	6	5	4	3	2	1	0

$PC \longleftarrow nn$
JP nn
1	1	0	0	0	0	1	1	C3
7	nn						0
15	nn						8

$\begin{rcases} PC \longleftarrow nn \end{rcases} \text {if } ccc = true$
1	1	ccc			0	1	0
7	nn						0
15	nn						8

$PC \longleftarrow HL$
JP (HL)
1	1	1	0	1	0	0	1	E9

$PC \longleftarrow IX$
JP (IX)
1	1	0	1	1	1	0	1	DD
1	1	1	0	1	0	0	1	E9

$PC \longleftarrow IY$
JP (IY)
1	1	1	1	1	1	0	1	FD
1	1	1	0	1	0	0	1	E9

Conditions
ccc	Abbrev	Condition	Flag
000	NZ	Non Zero	Z
001	Z	Zero	Z
010	NC	No Carry	C
011	C	Carry	C
100	PO	Parity Odd	P/V
101	PE	Parity Even	P/V
110	P	Sign Positive	S
111	M	Sign Negative	S

Jumps to 16bit registers

Although the instruction JP (HL) looks like it's using indirect addressing, it doesn't. It takes the address in HL as the new PC, so it should be read as if it's JP HL.

The same applies for JP (IX) and JP (IY) - the actual register is used not the value at that address.

Flags Affected

None.

Opcode Matrix

	Uncond	C	NC	Z	NZ	PE	PO	N	P
JP nn	JP nn C3nnnn310	JP C,nn DAnnnn310	JP NC,nn D2nnnn310	JP Z,nn CAnnnn310	JP NZ,nn C2nnnn310	JP PE,nn EAnnnn310	JP PO,nn E2nnnn310	JP N,nn FAnnnn310	JP P,nn F2nnnn310
JP (HL)	JP (HL) E914
JP (IX)	JP (IX) DDE928
JP (IY)	JP (IY) FDE928

Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count		Flow

2 - Jump Relative

7	6	5	4	3	2	1	0

$PC \longleftarrow PC + e$
JR e
0	0	0	1	1	0	0	0	18
e-2

$\begin{rcases} PC \longleftarrow (PC) + e \end{rcases} \text {if } cc = true$
JR cc, e
0	0	1	cc		0	0	0
e-2

$B \longleftarrow B - 1\\ \begin{rcases} PC \longleftarrow PC + e \end{rcases} \text{ if } B \not = 0$
DJNZ e
0	0	0	1	0	0	0	0	10
e-2

Conditions
cc	Abbrev	Condition	Flag
00	NZ	Non Zero	Z
01	Z	Zero	Z
10	NC	No Carry	C
11	C	Carry	C

Relative Jumps

For relative instructions the offset is taken from the address of the op code so is in the range -126 to 129. Assemblers usually account for the difference where the value in memory is e-2.

Timing

For JR then when a jump takes place then it takes 12(4,3,5) T-States whilst no jump 7(4,3) T-States.

For DJNZ if the jump takes place then it takes 13 (5,3,5) T-States. If no jump then 8 (5,3) T-States.

Flags Affected

None.

Opcode Matrix

	Uncond	C	NC	Z	NZ	B!=0
JR e	JR e 18nn212	JR C,e 38nn212	JR NC,e 30nn212	JR Z,e 28nn212	JR NZ,e 20nn212
DJNZ e						DJNZ e 10nn213

Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count		Flow

3 - Call subroutine

7	6	5	4	3	2	1	0

$(SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn$
CALL nn
1	1	0	0	1	1	0	1	CD
7	nn						0
15	nn						8

$\begin{rcases} (SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn \end{rcases} \text{ if } ccc = true$
CALL ccc, nn
1	1	ccc			1	0	0	CD
7	nn						0
15	nn						8

Conditions
ccc	Abbrev	Condition	Flag
000	NZ	Non Zero	Z
001	Z	Zero	Z
010	NC	No Carry	C
011	C	Carry	C
100	PO	Parity Odd	P/V
101	PE	Parity Even	P/V
110	P	Sign Positive	S
111	M	Sign Negative	S

Timing

All call operation's take 17 (4,3,4,3,3) T-States, except for the conditional ones when the condition has not been met. In those instances it takes 10(4,3,3) T-States.

Flags Affected

None.

Opcode Matrix

	Uncond	C	NC	Z	NZ	PE	PO	N	P
CALL nn	CALL nn CDnnnn317	CALL C,nn DCnnnn317	CALL NC,nn D4nnnn317	CALL Z,nn CCnnnn317	CALL NZ,nn C4nnnn317	CALL PE,nn ECnnnn317	CALL PO,nn E4nnnn317	CALL N,nn FCnnnn317	CALL P,nn F4nnnn317

Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count		Flow

4 - Return from Subroutine

7	6	5	4	3	2	1	0

$PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2$
RET
1	1	0	0	1	0	0	1

$\begin{rcases} PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2 \end{rcases} \text{ if } ccc = true$
RET ccc
1	1	ccc			0	0	0

Conditions
ccc	Abbrev	Condition	Flag
000	NZ	Non Zero	Z
001	Z	Zero	Z
010	NC	No Carry	C
011	C	Carry	C
100	PO	Parity Odd	P/V
101	PE	Parity Even	P/V
110	P	Sign Positive	S
111	M	Sign Negative	S

Timing

The unconditional RET takes 10 (4,3,3) T-States. The conditional RET takes 17(5,3,3) T-States if the condition is true and 5 T-States if false and no return was performed.

Flags Affected

None.

Opcode Matrix

	Uncond	C	NC	Z	NZ	PE	PO	N	P
RET	RET C9110	RET C D8111	RET NC D0111	RET Z C8111	RET NZ C0111	RET PE E8111	RET PO E0111	RET N F8111	RET P F0111

Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count		Flow

5 - RST

Invoke a Reset

RST performs a reset. Specifically it calls a routine at one of 8 addresses at the base of memory. It is the equivalent of performing a CALL to that address except the RST instruction is just 1 byte compared to 3 for CALL and is slightly faster.

$(SP-1) \longleftarrow PC_h \\(SP-2) \longleftarrow PC_l \\SP \longleftarrow SP-2 \\PC_h \longleftarrow 0\\PC_l \longleftarrow b*8$

7	6	5	4	3	2	1	0
1	1	b			1	1	1

Bits
Value		b
0		000
1		001
2		010
3		011
4		100
5		101
6		110
7		111

Issues with RST instructions

Assemblers use different conventions for the RST instruction. Some use numbers 0…7 whilst others use the address of the code invoked. They are all equivalent, as there are just 8 possible instruction codes.

Address	OP Code	RST Instruction			Action
0000	C7	RST 0			Reset machine
0008	CF	RST 1	RST 8		Operating System Specific
0010	D7	RST 2	RST $10	RST 16
0018	DF	RST 3	RST $18	RST 24
0020	E7	RST 4	RST $20	RST 32
0028	EF	RST 5	RST $28	RST 40
0030	F7	RST 6	RST $30	RST 48
0038	FF	RST 7	RST $38	RST 56	Interrupt Handler in Mode 1

Flags Affected

None.

Opcode Matrix

	Reset routine
	0	1	2	3	4	5	6	7
RST	RST 0 C7111	RST 1 CF111	RST 2 D7111	RST 3 DF111	RST 4 E7111	RST 5 EF111	RST 6 F7111	RST 7 FF111

Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count		Special

6 - Return from Interrupt

7	6	5	4	3	2	1	0

$PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2$
RETI
1	1	1	0	1	1	0	1	ED
0	1	0	0	1	1	0	1	4D

$PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2 \\ IFF_1 \longleftarrow IFF_2$
RETN
1	1	1	0	1	1	0	1	ED
0	1	0	0	0	1	0	1	45

Flags Affected

None.

Opcode Matrix

	RETI	RETN
Op	RETI ED4D214	RETN ED45214

Opcode Matrix Legend
Instruction Opcode hexSize bytesCycle count		Interrupt

Program Flow

Table of Contents

1 - Jump absolute

Jumps to 16bit registers

Flags Affected

Opcode Matrix

2 - Jump Relative

Relative Jumps

Timing

Flags Affected

Opcode Matrix

3 - Call subroutine

Timing

Flags Affected

Opcode Matrix

4 - Return from Subroutine

Timing

Flags Affected

Opcode Matrix

5 - RST

Issues with RST instructions

Flags Affected

Opcode Matrix

6 - Return from Interrupt

Flags Affected

Opcode Matrix

7	6	5	4	3	2	1	0

\(PC \longleftarrow nn\)
JP nn
1	1	0	0	0	0	1	1	C3
7	nn						0
15	nn						8

\(\begin{rcases} PC \longleftarrow nn \end{rcases} \text {if } ccc = true\)
1	1	ccc			0	1	0
7	nn						0
15	nn						8

\(PC \longleftarrow HL\)
JP (HL)
1	1	1	0	1	0	0	1	E9

\(PC \longleftarrow IX\)
JP (IX)
1	1	0	1	1	1	0	1	DD
1	1	1	0	1	0	0	1	E9

\(PC \longleftarrow IY\)
JP (IY)
1	1	1	1	1	1	0	1	FD
1	1	1	0	1	0	0	1	E9

7	6	5	4	3	2	1	0

\(PC \longleftarrow PC + e\)
JR e
0	0	0	1	1	0	0	0	18
e-2

\(\begin{rcases} PC \longleftarrow (PC) + e \end{rcases} \text {if } cc = true\)
JR cc, e
0	0	1	cc		0	0	0
e-2

\(B \longleftarrow B - 1\\ \begin{rcases} PC \longleftarrow PC + e \end{rcases} \text{ if } B \not = 0\)
DJNZ e
0	0	0	1	0	0	0	0	10
e-2

7	6	5	4	3	2	1	0

\((SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn\)
CALL nn
1	1	0	0	1	1	0	1	CD
7	nn						0
15	nn						8

\(\begin{rcases} (SP-1) \longleftarrow PC_h\\ (SP-2) \longleftarrow PC_l\\ SP \longleftarrow SP-2\\ PC \longleftarrow nn \end{rcases} \text{ if } ccc = true\)
CALL ccc, nn
1	1	ccc			1	0	0	CD
7	nn						0
15	nn						8

7	6	5	4	3	2	1	0

\(PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2\)
RET
1	1	0	0	1	0	0	1

\(\begin{rcases} PC_l \longleftarrow (SP) \\ PC_h \longleftarrow (SP+1) \\ SP \longleftarrow SP+2 \end{rcases} \text{ if } ccc = true\)
RET ccc
1	1	ccc			0	0	0