| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| \(PC \longleftarrow nn\) | ||||||||
| JP nn | ||||||||
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | C3 |
| 7 | nn | 0 | ||||||
| 15 | 8 | |||||||
| \(\begin{rcases} PC \longleftarrow nn \end{rcases} \text {if } ccc = true\) | ||||||||
| 1 | 1 | ccc | 0 | 1 | 0 | |||
| 7 | nn | 0 | ||||||
| 15 | 8 | |||||||
| \(PC \longleftarrow HL\) | ||||||||
| JP (HL) | ||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | E9 |
| \(PC \longleftarrow IX\) | ||||||||
| JP (IX) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | E9 |
| \(PC \longleftarrow IY\) | ||||||||
| JP (IY) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | E9 |
| ccc | Abbrev | Condition | Flag |
|---|---|---|---|
| 000 | NZ | Non Zero | Z |
| 001 | Z | Zero | |
| 010 | NC | No Carry | C |
| 011 | C | Carry | |
| 100 | PO | Parity Odd | P/V |
| 101 | PE | Parity Even | |
| 110 | P | Sign Positive | S |
| 111 | M | Sign Negative |
Jumps to 16bit registers
Although the instruction JP (HL) looks like it's using indirect addressing, it doesn't.
It takes the address in HL as the new PC, so it should be read as if it's
JP HL.
The same applies for JP (IX) and JP (IY) - the actual register is used not the value at that address.
Flags Affected
| None. |
Opcode Matrix
| Uncond | C | NC | Z | NZ | PE | PO | N | P | |
|---|---|---|---|---|---|---|---|---|---|
| JP nn |
JP nn
C3nnnn310 |
JP C,nn
DAnnnn310 |
JP NC,nn
D2nnnn310 |
JP Z,nn
CAnnnn310 |
JP NZ,nn
C2nnnn310 |
JP PE,nn
EAnnnn310 |
JP PO,nn
E2nnnn310 |
JP N,nn
FAnnnn310 |
JP P,nn
F2nnnn310 |
| JP (HL) |
JP (HL)
E914 |
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| JP (IX) |
JP (IX)
DDE928 |
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| JP (IY) |
JP (IY)
FDE928 |
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Instruction
Opcode hexSize bytesCycle count
| Flow |