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\(A \longleftarrow (n)\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | DB |
| n | ||||||||
This instruction places n onto the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of the Accumulator also appear on the top half (A8…A15) of the address bus at this time. One byte from the selected port is placed on the data bus and written to the Accumulator (Register A).
| None. |
| A | |
|---|---|
| IN (n) |
IN A,(n)
DBnn211 |
|
Instruction
Opcode hexSize bytesCycle count
| Special |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| \(r \longleftarrow (C)\) | ||||||||
| IN r, (C) | ||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | r | 0 | 0 | 0 | |||
| \(F \longleftarrow (C)\) | ||||||||
| IN F, (C) | ||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 70 |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
The contents of Register C are placed on the bottom half (A0…7) of the address bus to select the I/O device at one of 256 possible ports. The contents of Register B are placed on the top half (A8…A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to register r in the CPU.
There is an undocumented code where r=%110 which sets the flag register.
This is actually documented in Zilog's Z80 CPU User Manual, 2016 edition Page 296. For this reason it's included on this page and not in the Undocumented instruction section.
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if input data is negative | ||||||||
| z | set if input data is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity is even, reset if odd | ||||||||
| n | reset |
| A | B | C | D | E | H | L | F | |
|---|---|---|---|---|---|---|---|---|
| IN (C) |
IN A,(C)
ED7B212 |
IN B,(C)
ED40212 |
IN C,(C)
ED48212 |
IN D,(C)
ED50212 |
IN E,(C)
ED58212 |
IN H,(C)
ED60212 |
IN L,(C)
ED68212 |
IN F,(C)
ED70212 |
|
Instruction
Opcode hexSize bytesCycle count
| Special | Undocumented |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| \((C) \longleftarrow r\) | ||||||||
| OUT (C), r | ||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | r | 0 | 0 | 1 | |||
| \((C) \longleftarrow F\) | ||||||||
| OUT (C), F | ||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 71 |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
The contents of Register C are placed on the bottom half (A0…7) of the address bus to select the I/O device at one of 256 possible ports.
The contents of Register B are placed on the top half (A8…A15) of the address bus at this time.
Then the byte contained in r is placed on the data bus and written to the selected peripheral device.
There is an undocumented code where r=%110 which writes the flag register.
Unlike it's IN F, (C) counterpart, this instruction is completely undocumented, but it's here not in the undocumented section to be consistent.
| None. |
| A | B | C | D | E | H | L | F | |
|---|---|---|---|---|---|---|---|---|
| OUT (C) |
OUT (C),A
ED79212 |
OUT (C),B
ED41212 |
OUT (C),C
ED49212 |
OUT (C),D
ED51212 |
OUT (C),E
ED59212 |
OUT (C),H
ED61212 |
OUT (C),L
ED69212 |
OUT (C),F
ED71212 |
|
Instruction
Opcode hexSize bytesCycle count
| Special | Undocumented |
\((n) \longleftarrow A\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | D3 |
| n | ||||||||
This instruction places n onto the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.
The contents of the Accumulator also appear on the top half (A8…A15) of the address bus at this time.
Then the byte contained in the Accumulator is placed on the data bus and written to the selected peripheral device.
| None. |
| A | |
|---|---|
| OUT (n) |
OUT (n),A
D3nn211 |
|
Instruction
Opcode hexSize bytesCycle count
| Special |
\(\begin{rcases} (HL) \longleftarrow (C)\\HL \longleftarrow HL+1 \text{ if } D = 0\\HL \longleftarrow HL-1 \text{ if } D = 1\\B \longleftarrow B-1 \end{rcases} \text{repeat while } L=1 \And B \not = 0\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 1 | 0 | 1 | L | D | 0 | 1 | 0 |
D 0=Increment, 1=Decrement HL after each iteration
L If set then if \(B \not = 0\) then \(PC \longleftarrow PC-2\) so that the instruction is repeated.
The contents of Register C are placed on the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.
Register B can be used as a byte counter, and its contents are placed on the top half (A8…15) of the address bus at this time.
Then one byte from the selected port is placed on the data bus and written to the CPU.
The contents of the HL register pair are then placed on the address bus and the input byte is written to the corresponding location of memory.
Finally, the byte counter is decremented and register pair HL is incremented.
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| z | set if B = 0, always true for repeat operations | ||||||||
| n | set |
| Increment | Decrement | |
|---|---|---|
| Single |
INI
EDA2216 |
IND
EDAA216 |
| Repeat |
INIR
EDB2221 |
INDR
EDBA221 |
|
Instruction
Opcode hexSize bytesCycle count
| Special |
\(\begin{rcases} (C) \longleftarrow (HL)\\HL \longleftarrow HL+1 \text{ if } D = 0\\HL \longleftarrow HL-1 \text{ if } D = 1\\B \longleftarrow B-1 \end{rcases} \text{repeat while } L=1 \And B \not = 0\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 1 | 0 | 1 | L | D | 0 | 1 | 1 |
D 0=Increment, 1=Decrement HL after each iteration
L If set then if \(B \not = 0\) then \(PC \longleftarrow PC-2\) so that the instruction is repeated.
The contents of Register C are placed on the bottom half (A0…A7) of the address bus to select the I/O device at one of 256 possible ports.
Register B can be used as a byte counter, and its contents are placed on the top half (A8…15) of the address bus at this time.
Then one byte from the address pointed to by HL is placed on the data bus and written to the port.
Finally, the byte counter is decremented and register pair HL is incremented.
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| z | set if B = 0, always true for repeat operations | ||||||||
| n | set |
| Increment | Decrement | |
|---|---|---|
| Single |
OUTI
EDA3216 |
OUTD
EDAB216 |
| Repeat |
OUTIR
EDB3221 |
OUTDR
EDBB221 |
|
Instruction
Opcode hexSize bytesCycle count
| Special |