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Rotate and Shift
Rotate Shift instructions
Table of Contents
1 - RL Rotate bits left with Carry
Rotate bits left with carry
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RLA | ||||||||
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 17 |
| RL r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 1 | 0 | r | |||
| RL (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 16 |
| RL (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 16 |
| RL (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 16 |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd | ||||||||
| c | data from bit 7 of source register |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
|---|---|---|---|---|---|---|---|---|---|---|
| RL |
RLA
1714 |
|
|
|
|
|
|
|
|
|
| RL |
RL A
CB1728 |
RL B
CB1028 |
RL C
CB1128 |
RL D
CB1228 |
RL E
CB1328 |
RL H
CB1428 |
RL L
CB1528 |
RL (HL)
CB16215 |
RL (IX+d)
DDCBnn16423 |
RL (IY+d)
FDCBnn16423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
2 - RLC Rotate bits left with Carry
Rotate bits left with carry
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RLCA | ||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 07 |
| RLC r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 0 | 0 | r | |||
| RLC (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 06 |
| RLC (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 06 |
| RLC (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 06 |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd | ||||||||
| c | data from bit 7 of source register |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
|---|---|---|---|---|---|---|---|---|---|---|
| RLC |
RLCA
0714 |
|
|
|
|
|
|
|
|
|
| RLC |
RLC A
CB0728 |
RLC B
CB0028 |
RLC C
CB0128 |
RLC D
CB0228 |
RLC E
CB0328 |
RLC H
CB0428 |
RLC L
CB0528 |
RLC (HL)
CB0628 |
RLC (IX+d)
DDCBnn06423 |
RLC (IY+d)
FDCBnn06423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
3 - RR Rotate bits right with Carry
Rotate bits right with carry
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RRA | ||||||||
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1F |
| RR r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 1 | 1 | r | |||
| RR (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1E |
| RR(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1E |
| RR (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1E |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd | ||||||||
| c | data from bit 0 of source register |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
|---|---|---|---|---|---|---|---|---|---|---|
| RR |
RRA
1F14 |
|
|
|
|
|
|
|
|
|
| RR |
RR A
CB1F28 |
RR B
CB1828 |
RR C
CB1928 |
RR D
CB1A28 |
RR E
CB1B28 |
RR H
CB1C28 |
RR L
CB1D28 |
RR (HL)
CB1E215 |
RR (IX+d)
DDCBnn1E423 |
RR (IY+d)
FDCBnn1E423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
4 - RRC Rotate bits right with Carry
Rotate bits left with carry
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RRCA | ||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0F |
| RRC r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 0 | 1 | r | |||
| RRC (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0E |
| RRC (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0E |
| RRC (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0E |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd | ||||||||
| c | data from bit 0 of source register |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
|---|---|---|---|---|---|---|---|---|---|---|
| RRC |
RRCA
0F14 |
|
|
|
|
|
|
|
|
|
| RRC |
RRC A
CB0F28 |
RRC B
CB0828 |
RRC C
CB0928 |
RRC D
CB0A28 |
RRC E
CB0B28 |
RRC H
CB0C28 |
RRC L
CB0D28 |
RRC (HL)
CB0E215 |
RRC (IX+d)
DDCBnn0E423 |
RRC (IY+d)
FDCBnn0E423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
5 - SLA Shift bits left with Carry
Shift bits left with carry
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| SLA r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 1 | 0 | 0 | r | |||
| SLA (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 26 |
| SLA (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 26 |
| SLA (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 26 |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd | ||||||||
| c | data from bit 7 of source register |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
|---|---|---|---|---|---|---|---|---|---|---|
| SLA |
SLA A
CB2728 |
SLA B
CB2028 |
SLA C
CB2128 |
SLA D
CB2228 |
SLA E
CB2328 |
SLA H
CB2428 |
SLA L
CB2528 |
SLA (HL)
CB26215 |
SLA (IX+d)
DDCBnn26423 |
SLA (IY+d)
FDCBnn26423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
6 - SRA Rotate bits right with Carry
Rotate bits right with carry, bit 7 remains unchanged
An arithmetic shift right 1 bit position is performed on the contents of operand. The contents of bit 0 are copied to the Carry flag and the previous contents of bit 7 remain unchanged.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| SRA r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 1 | 0 | 1 | r | |||
| SRA (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 2E |
| SRA (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 2E |
| SRA (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 2E |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd | ||||||||
| c | data from bit 0 of source register |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
|---|---|---|---|---|---|---|---|---|---|---|
| SRA |
SRA A
CB2F28 |
SRA B
CB2828 |
SRA C
CB2928 |
SRA D
CB2A28 |
SRA E
CB2B28 |
SRA H
CB2C28 |
SRA L
CB2D28 |
SRA (HL)
CB2E215 |
SRA (IX+d)
DDCBnn2E423 |
SRA (IY+d)
FDCBnn2E423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
7 - SRL Rotate bits right with Carry
Rotate bits right with carry, bit 7 is reset
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| SRL r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 1 | 1 | 1 | r | |||
| SRL (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 3E |
| SRL (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 3E |
| SRL (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 3E |
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd | ||||||||
| c | data from bit 0 of source register |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
|---|---|---|---|---|---|---|---|---|---|---|
| SRL |
SRL A
CB3F28 |
SRL B
CB3828 |
SRL C
CB3928 |
SRL D
CB3A28 |
SRL E
CB3B28 |
SRL H
CB3C28 |
SRL L
CB3D28 |
SRL (HL)
CB3E215 |
SRL (IX+d)
DDCBnn3E423 |
SRL (IY+d)
FDCBnn3E423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
8 - RLD
Rotate bit pairs in A and (HL) left
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 6F |
The contents of the low-order four bits (bits 3, 2, 1, and 0) of the memory location (HL) are copied to the high-order four bits (7, 6, 5, and 4) of that same memory location; the previous contents of those high-order four bits are copied to the low-order four bits of the Accumulator (Register A); and the previous contents of the low-order four bits of the Accumulator are copied to the low-order four bits of memory location (HL). The contents of the high-order bits of the Accumulator are unaffected.
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd |
Opcode Matrix
| (HL) | |
|---|---|
| Op |
RLD (HL)
ED6F218 |
|
Instruction
Opcode hexSize bytesCycle count
| Memory |
9 - RRD
Rotate bit pairs in A and (HL) right
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 67 |
The contents of the low-order four bits (bits 3, 2, 1, and 0) of memory location (HL) are copied to the low-order four bits of the Accumulator (Register A). The previous contents of the low-order four bits of the Accumulator are copied to the high-order four bits (7, 6, 5, and 4) of location (HL); and the previous contents of the high-order four bits of (HL) are copied to the low-order four bits of (HL). The contents of the high-order bits of the Accumulator are unaffected.
Flags Affected
| Flags |
| ||||||||
|---|---|---|---|---|---|---|---|---|---|
| s | set if result negative | ||||||||
| z | set if result is 0 | ||||||||
| h | reset | ||||||||
| p/v | set if parity even, reset if parity odd |
Opcode Matrix
| (HL) | |
|---|---|
| Op |
RRD (HL)
ED67218 |
|
Instruction
Opcode hexSize bytesCycle count
| Memory |