Undocumented Instructions
Undocumented instructions - use with care
Table of Contents
Like most early microprocessors, the Z80 has it's own set of undocumented instructions.
Most of these either do something that's not useful, or they do something that would at first seem
to be odd in why they were implemented in the first place.
In most instances, they exist due to how the processor is implemented in silicon.
Where an instruction is decoded, there are free bits so if something tried to use that code then
the processor would just do as it's told as it wouldn't know otherwise.
Be aware, these usually work on a physical chip due to it requiring the actual instruction decoding to
provide these instructions.
They will most likely not work in an emulator as they would perform the decoding in software using lookup
tables, so wouldn't implement anything that's not documented.
These may or may not work on actual chips.
For example, on the 6502 there were plenty of undocumented instructions that were replaced in the 65C02 with
NOP instructions.
These are provided here for reference only.
Overview
Most of the undocumented instructions fall under some simple rules:
CB
Only codes 0xCB30…0xCB37 are undocumented but implement a Shift Logical Left
instruction where bit 0 is set post shift.
DDCB & FDCB
For opcodes with the 0xDDCB and 0xFDCB prefixes the instructions store the result in one of the 8-bit registers
based on the lower 3 bits of the opcode:
B=000, C=001, D=010, E=011, H=100, L=101 and A=111.
The officially documented codes all have 110 as the lower 3 bits and do not store the result in any register.
All of these instructions with the 0xDDCB prefix operate against the IX register (IY for 0xFDBC).
The only exception to this rule is opcodes 0x40…0x7F which are the bit text operations.
As these only test the memory location they do not create a result so all the undocumented versions are
identical to the official instructions.
DD & FD
Officially the 0xDD and 0xFD prefixes cause any instruction that references (HL) to instead work
against the IX & IY registers with a displacement, 0xDD for IX and 0xFD for IY.
The undocumented instructions allows for instructions that refer to just H or L can also be used to access
the upper or lower 8-bit components of IX and IY themselves.
ED
There are a few undocumented instructions with this prefix, but they simply emulate existing instructions.
The exception to this are the IN F, (C) and OUT (C), F instructions which are
described below.
When is undocumented actually documented?
One oddity is the undocumented IN F,(C)0xED70 instruction
which performs an IN from an I/O port but stores the result into the Flags register.
This instruction is actually documented in Zilogs own documentation (2016 PDF).
For this reason, that instruction is listed on the IN r, (C) page and not in this
section.
It's OUT (C), F0xED71 equivalent is listed under OUT (C), r for consistency, even though that
instruction is completely undocumented.
1 - Dual Shift Operations
Undocumented instructions that perform two actions at the same time
There are a few undocumented instructions that performs an action and then copies the result into a register.
For example the official RLC (IX+nn)0xDDCBnn06 instruction operates on a specific memory address,
however the undocumented RLC B,(IX+nn)0xDDCBnn00 instruction does the same thing but then
copies the result into the B register.
1.1 - RL Rotate bits left with Carry and store in register
Undocumented Rotate bits left with carry and store in register
This instruction performs an RL (IX+dd) or RL (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| RL r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 1 | 0 | r |
| |
| RL r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 1 | 0 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
RL A,(IX+d)
DDCBnn17
|
RL B,(IX+d)
DDCBnn10
|
RL C,(IX+d)
DDCBnn11
|
RL D,(IX+d)
DDCBnn12
|
RL E,(IX+d)
DDCBnn13
|
RL H,(IX+d)
DDCBnn14
|
RL L,(IX+d)
DDCBnn15
|
| (IY+d) |
RL A,(IY+d)
FDCBnn17
|
RL B,(IY+d)
FDCBnn10
|
RL C,(IY+d)
FDCBnn11
|
RL D,(IY+d)
FDCBnn12
|
RL E,(IY+d)
FDCBnn13
|
RL H,(IY+d)
FDCBnn14
|
RL L,(IY+d)
FDCBnn15
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
1.2 - RLC Rotate bits left with Carry and store in register
Undocumented Rotate bits left with carry and store in register
This instruction performs an RLC (IX+dd) or RLC (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| RLC r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 0 | 0 | r |
| |
| RLC r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 0 | 0 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
RLC A,(IX+d)
DDCBnn07
|
RLC B,(IX+d)
DDCBnn00
|
RLC C,(IX+d)
DDCBnn01
|
RLC D,(IX+d)
DDCBnn02
|
RLC E,(IX+d)
DDCBnn03
|
RLC H,(IX+d)
DDCBnn04
|
RLC L,(IX+d)
DDCBnn05
|
| (IY+d) |
RLC A,(IY+d)
FDCBnn07
|
RLC B,(IY+d)
FDCBnn00
|
RLC C,(IY+d)
FDCBnn01
|
RLC D,(IY+d)
FDCBnn02
|
RLC E,(IY+d)
FDCBnn03
|
RLC H,(IY+d)
FDCBnn04
|
RLC L,(IY+d)
FDCBnn05
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
1.3 - RR Rotate bits right with Carry and store in register
Undocumented Rotate bits right with carry and store in register
This instruction performs an RR (IX+dd) or RR (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| RR r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 1 | 1 | r |
| |
| RR r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 1 | 1 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
RR A,(IX+d)
DDCBnn1F
|
RR B,(IX+d)
DDCBnn18
|
RR C,(IX+d)
DDCBnn19
|
RR D,(IX+d)
DDCBnn1A
|
RR E,(IX+d)
DDCBnn1B
|
RR H,(IX+d)
DDCBnn1C
|
RR L,(IX+d)
DDCBnn1D
|
| (IY+d) |
RR A,(IY+d)
FDCBnn1F
|
RR B,(IY+d)
FDCBnn18
|
RR C,(IY+d)
FDCBnn19
|
RR D,(IY+d)
FDCBnn1A
|
RR E,(IY+d)
FDCBnn1B
|
RR H,(IY+d)
FDCBnn1C
|
RR L,(IY+d)
FDCBnn1D
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
1.4 - RRC Rotate bits right with Carry and store in register
Undocumented Rotate bits right with carry and store in register
This instruction performs an RRC (IX+dd) or RRC (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| RRC r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 0 | 1 | r |
| |
| RRC r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 0 | 1 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
RRC A,(IX+d)
DDCBnn0F
|
RRC B,(IX+d)
DDCBnn08
|
RRC C,(IX+d)
DDCBnn09
|
RRC D,(IX+d)
DDCBnn0A
|
RRC E,(IX+d)
DDCBnn0B
|
RRC H,(IX+d)
DDCBnn0C
|
RRC L,(IX+d)
DDCBnn0D
|
| (IY+d) |
RRC A,(IY+d)
FDCBnn0F
|
RRC B,(IY+d)
FDCBnn08
|
RRC C,(IY+d)
FDCBnn09
|
RRC D,(IY+d)
FDCBnn0A
|
RRC E,(IY+d)
FDCBnn0B
|
RRC H,(IY+d)
FDCBnn0C
|
RRC L,(IY+d)
FDCBnn0D
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
1.5 - SLA Shift bits left with Carry and store in register
Undocumented Shift bits left with carry and store in register
This instruction performs an SLA (IX+dd) or SLA (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| SLA r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 0 | 0 | r |
| |
| SLA r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 0 | 0 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
SLA A,(IX+d)
DDCBnn27
|
SLA B,(IX+d)
DDCBnn20
|
SLA C,(IX+d)
DDCBnn21
|
SLA D,(IX+d)
DDCBnn22
|
SLA E,(IX+d)
DDCBnn23
|
SLA H,(IX+d)
DDCBnn24
|
SLA L,(IX+d)
DDCBnn25
|
| (IY+d) |
SLA A,(IY+d)
FDCBnn27
|
SLA B,(IY+d)
FDCBnn20
|
SLA C,(IY+d)
FDCBnn21
|
SLA D,(IY+d)
FDCBnn22
|
SLA E,(IY+d)
FDCBnn23
|
SLA H,(IY+d)
FDCBnn24
|
SLA L,(IY+d)
FDCBnn25
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
1.6 - SLL Shift left Logical and store in register
Undocumented Shift left logical and store in register
This instruction performs an SLL (IX+dd) or SLL (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
Note: This is an undocumented extension to an undocumented instruction.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| SLL r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 1 | 0 | r |
| |
| SLL r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 1 | 0 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
SLL A,(IX+d)
DDCBnn37
|
SLL B,(IX+d)
DDCBnn30
|
SLL C,(IX+d)
DDCBnn31
|
SLL D,(IX+d)
DDCBnn32
|
SLL E,(IX+d)
DDCBnn33
|
SLL H,(IX+d)
DDCBnn34
|
SLL L,(IX+d)
DDCBnn35
|
| (IY+d) |
SLL A,(IY+d)
FDCBnn37
|
SLL B,(IY+d)
FDCBnn30
|
SLL C,(IY+d)
FDCBnn31
|
SLL D,(IY+d)
FDCBnn32
|
SLL E,(IY+d)
FDCBnn33
|
SLL H,(IY+d)
FDCBnn34
|
SLL L,(IY+d)
FDCBnn35
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
1.7 - SRA Rotate bits right with Carry and store in register
Undocumented Rotate bits right with carry and store in register
This instruction performs an SRA (IX+dd) or SRA (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| SRA r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 0 | 1 | r |
| |
| SRA r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 0 | 1 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
SRA A,(IX+d)
DDCBnn2F
|
SRA B,(IX+d)
DDCBnn28
|
SRA C,(IX+d)
DDCBnn29
|
SRA D,(IX+d)
DDCBnn2A
|
SRA E,(IX+d)
DDCBnn2B
|
SRA H,(IX+d)
DDCBnn2C
|
SRA L,(IX+d)
DDCBnn2D
|
| (IY+d) |
SRA A,(IY+d)
FDCBnn2F
|
SRA B,(IY+d)
FDCBnn28
|
SRA C,(IY+d)
FDCBnn29
|
SRA D,(IY+d)
FDCBnn2A
|
SRA E,(IY+d)
FDCBnn2B
|
SRA H,(IY+d)
FDCBnn2C
|
SRA L,(IY+d)
FDCBnn2D
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
1.8 - SRL Rotate bits right with Carry and store in register
Undocumented Rotate bits right with carry and store in register
This instruction performs an SRL (IX+dd) or SRL (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| SRL r,(IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 1 | 1 | r |
| |
| SRL r,(IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 1 | 1 | 1 | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
Opcode Matrix
| A | B | C | D | E | H | L |
|---|
| (IX+d) |
SRL A,(IX+d)
DDCBnn3F
|
SRL B,(IX+d)
DDCBnn38
|
SRL C,(IX+d)
DDCBnn39
|
SRL D,(IX+d)
DDCBnn3A
|
SRL E,(IX+d)
DDCBnn3B
|
SRL H,(IX+d)
DDCBnn3C
|
SRL L,(IX+d)
DDCBnn3D
|
| (IY+d) |
SRL A,(IY+d)
FDCBnn3F
|
SRL B,(IY+d)
FDCBnn38
|
SRL C,(IY+d)
FDCBnn39
|
SRL D,(IY+d)
FDCBnn3A
|
SRL E,(IY+d)
FDCBnn3B
|
SRL H,(IY+d)
FDCBnn3C
|
SRL L,(IY+d)
FDCBnn3D
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
2 - IX and IY registers
Undocumented instructions for IX and IY registers
If an opcode works with the Registers HL, H or L then if that opcode is prefixed by 0xDD then it will also
work on the appropriate IX, IXh or IXl registers, with some exceptions.
The 0xFD prefix would also work but for the IY, IYh or IYl registers
The exceptions are instructions like LD H,IXh or LD L,IYh where it
isn't clear from the opcode which register the 0xFD or 0xDD prefix should operate against.
2.1 - LD IX undocumented instructions
Undocumented instructions for LD IX
Opcode Matrix
| A | B | C | D | E | n | IXh | IXl |
|---|
| A |
|
|
|
|
|
|
LD A,IXh
DD7C
|
LD A,IXl
DD7D
|
| B |
|
|
|
|
|
|
LD B,IXh
DD44
|
LD B,IXl
DD45
|
| C |
|
|
|
|
|
|
LD C,IXh
DD4C
|
LD C,IXl
DD4D
|
| D |
|
|
|
|
|
|
LD D,IXh
DD54
|
LD D,IXl
DD55
|
| E |
|
|
|
|
|
|
LD E,IXh
DD5C
|
LD E,IXl
DD5D
|
| IXh |
LD IXh,A
DD67
|
LD IXh,B
DD60
|
LD IXh,C
DD61
|
LD IXh,D
DD62
|
LD IXh,E
DD63
|
LD IXh,n
DD26nn
|
LD IXh,IHh
DD64
|
LD IXh,IHl
DD65
|
| IXl |
LD IXl,A
DD6F
|
LD IXl,B
DD68
|
LD IXl,C
DD69
|
LD IXl,D
DD6A
|
LD IXl,E
DD6B
|
LD IXl,n
DD2Enn
|
LD IXl,IHh
DD6C
|
LD IXl,IHl
DD6D
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
2.2 - LD IY undocumented instructions
Undocumented instructions for LD IY
Opcode Matrix
| A | B | C | D | E | n | IYh | IYl |
|---|
| A |
|
|
|
|
|
|
LD A,IYh
FD7C
|
LD A,IYl
FD7D
|
| B |
|
|
|
|
|
|
LD B,IYh
FD44
|
LD B,IYl
FD45
|
| C |
|
|
|
|
|
|
LD C,IYh
FD4C
|
LD C,IYl
FD4D
|
| D |
|
|
|
|
|
|
LD D,IYh
FD54
|
LD D,IYl
FD55
|
| E |
|
|
|
|
|
|
LD E,IYh
FD5C
|
LD E,IYl
FD5D
|
| IYh |
LD IYh,A
FD67
|
LD IYh,B
FD60
|
LD IYh,C
FD61
|
LD IYh,D
FD62
|
LD IYh,E
FD63
|
LD IYh,n
FD26nn
|
LD IYh,IHh
FD64
|
LD IYh,IHl
FD65
|
| IYl |
LD IYl,A
FD6F
|
LD IYl,B
FD68
|
LD IYl,C
FD69
|
LD IYl,D
FD6A
|
LD IYl,E
FD6B
|
LD IYl,n
FD2Enn
|
LD IYl,IHh
FD6C
|
LD IYl,IHl
FD6D
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
2.3 - Undocumented Math instructions with the IX register
Undocumented math instructions for IX register
Opcode Matrix
| INC | DEC | ADD A | ADC A | SUB | SBC A | AND | XOR | OR | CP |
|---|
| IXh |
INC IXh
DD24
|
DEC IXh
DD25
|
ADD A,IXh
DD84
|
ADC A,IXh
DD8C
|
SUB IXh
DD94
|
SBC A,IXh
DD9C
|
AND IXh
DDA4
|
XOR IXh
DDAC
|
OR IXh
DDB4
|
CP IXh
DDBC
|
| IXl |
INC IXl
DD2C
|
DEC IXl
DD2D
|
ADD A,IXl
DD85
|
ADC A,IXl
DD8D
|
SUB IXl
DD95
|
SBC A,IXl
DD9D
|
AND IXl
DDA5
|
XOR IXl
DDAD
|
OR IXl
DDB5
|
CP IXl
DDBD
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
2.4 - Undocumented Math instructions with the IY register
Undocumented math instructions for IY register
Opcode Matrix
| INC | DEC | ADD A | ADC A | SUB | SBC A | AND | XOR | OR | CP |
|---|
| IYh |
INC IYh
FD24
|
DEC IYh
FD25
|
ADD A,IYh
FD84
|
ADC A,IYh
FD8C
|
SUB IYh
FD94
|
SBC A,IYh
FD9C
|
AND IYh
FDA4
|
XOR IYh
FDAC
|
OR IYh
FDB4
|
CP IYh
FDBC
|
| IYl |
INC IYl
FD2C
|
DEC IYl
FD2D
|
ADD A,IYl
FD85
|
ADC A,IYl
FD8D
|
SUB IYl
FD95
|
SBC A,IYl
FD9D
|
AND IYl
FDA5
|
XOR IYl
FDAD
|
OR IYl
FDB5
|
CP IYl
FDBD
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
3 - SLL Shift Left Logical
Undocumented instruction to perform a logical left shift
The block CB30…CB37 is missing from the official list.
These instructions, usually denoted by the mnemonic SLL, Shift Left Logical, shift left the operand and make bit 0
always one.
These instructions are quite commonly used.
For example, Bounder and Enduro Racer use them.
Some documents list this as SL1 instead of SLL due to it setting bit 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| SLL r |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 0 | 0 | r |
| |
| SLL (HL) |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 06 |
| |
| SLL (IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 06 |
| |
| SLL (IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 06 |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Opcode Matrix
| A | B | C | D | E | H | L | (HL) | (IX+dd) | (IY+dd) |
|---|
| SLL |
SLL A
CB37
|
SLL B
CB30
|
SLL C
CB31
|
SLL D
CB32
|
SLL E
CB33
|
SLL H
CB34
|
SLL L
CB35
|
SLL (HL)
CB36
|
SLL (IX+dd)
DDCBnn36
|
SLL (IY+dd)
FDCBnn36
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
4 - Test bit in (IX+d)
Undocumented BIT n,(IX+d)
Similar to the RES and SET instructions, there are undocumented instructions for
BIT.
Unlike the other, as BIT only tests a bit and does not change anything, these opcodes have the same behaviour to
the officially documented BIT instruction.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| |
| \(Z \longleftarrow \overline{(IX+d)_b}\) |
| BIT b, (IX+d) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 1 | b | r |
| |
| \(Z \longleftarrow \overline{(IY+d)_b}\) |
| BIT b, (IY+d) |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 0 | 1 | b | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Bits
| Value | b |
| 0 | 000 |
| 1 | 001 |
| 2 | 010 |
| 3 | 011 |
| 4 | 100 |
| 5 | 101 |
| 6 | 110 |
| 7 | 111 |
Z is set if the specified bit in the source is 0, otherwise it is cleared.
r=%110 does exist, it is the official, documented operation.
5 - RES Reset bit in (IX+d) and copy into register r
Undocumented Reset bit in (IX+d) and copy into register r
There are a few undocumented instructions that performs an action and then copies the result into a register.
For example the official RES 0,(IX+nn) instruction resets bit 0 on a specific memory address,
however the undocumented RES B,0,(IX+nn)0xDDCBnn00 instruction does the same thing but then
copies the result into the B register.
\((IX+d)_b \longleftarrow 0 \\ r \longleftarrow (IX+d)\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 1 | 0 | b | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Bits
| Value | b |
| 0 | 000 |
| 1 | 001 |
| 2 | 010 |
| 3 | 011 |
| 4 | 100 |
| 5 | 101 |
| 6 | 110 |
| 7 | 111 |
Z is set if the specified bit in the source is 0, otherwise it is cleared.
The result is stored both in memory and the specified register.
r=%110 does exist, it is the official documented operation with no auto-copy to a register.
Opcode Matrix
| BIT 0 | BIT 1 | BIT 2 | BIT 3 | BIT 4 | BIT 5 | BIT 6 | BIT 7 |
|---|
| A |
RES A,0,(IX+nn)
DDCBnn87
|
RES A,1,(IX+nn)
DDCBnn8F
|
RES A,2,(IX+nn)
DDCBnn97
|
RES A,3,(IX+nn)
DDCBnn9F
|
RES A,4,(IX+nn)
DDCBnnA7
|
RES A,5,(IX+nn)
DDCBnnAF
|
RES A,6,(IX+nn)
DDCBnnB7
|
RES A,7,(IX+nn)
DDCBnnBF
|
| B |
RES B,0,(IX+nn)
DDCBnn80
|
RES B,1,(IX+nn)
DDCBnn88
|
RES B,2,(IX+nn)
DDCBnn90
|
RES B,3,(IX+nn)
DDCBnn98
|
RES B,4,(IX+nn)
DDCBnnA0
|
RES B,5,(IX+nn)
DDCBnnA8
|
RES B,6,(IX+nn)
DDCBnnB0
|
RES B,7,(IX+nn)
DDCBnnB8
|
| C |
RES C,0,(IX+nn)
DDCBnn81
|
RES C,1,(IX+nn)
DDCBnn89
|
RES C,2,(IX+nn)
DDCBnn91
|
RES C,3,(IX+nn)
DDCBnn99
|
RES C,4,(IX+nn)
DDCBnnA1
|
RES C,5,(IX+nn)
DDCBnnA9
|
RES C,6,(IX+nn)
DDCBnnB1
|
RES C,7,(IX+nn)
DDCBnnB9
|
| D |
RES D,0,(IX+nn)
DDCBnn82
|
RES D,1,(IX+nn)
DDCBnn8A
|
RES D,2,(IX+nn)
DDCBnn92
|
RES D,3,(IX+nn)
DDCBnn9A
|
RES D,4,(IX+nn)
DDCBnnA2
|
RES D,5,(IX+nn)
DDCBnnAA
|
RES D,6,(IX+nn)
DDCBnnB2
|
RES D,7,(IX+nn)
DDCBnnBA
|
| E |
RES E,0,(IX+nn)
DDCBnn83
|
RES E,1,(IX+nn)
DDCBnn8B
|
RES E,2,(IX+nn)
DDCBnn93
|
RES E,3,(IX+nn)
DDCBnn9B
|
RES E,4,(IX+nn)
DDCBnnA3
|
RES E,5,(IX+nn)
DDCBnnAB
|
RES E,6,(IX+nn)
DDCBnnB3
|
RES E,7,(IX+nn)
DDCBnnBB
|
| H |
RES H,0,(IX+nn)
DDCBnn84
|
RES H,1,(IX+nn)
DDCBnn8C
|
RES H,2,(IX+nn)
DDCBnn94
|
RES H,3,(IX+nn)
DDCBnn9C
|
RES H,4,(IX+nn)
DDCBnnA4
|
RES H,5,(IX+nn)
DDCBnnAC
|
RES H,6,(IX+nn)
DDCBnnB4
|
RES H,7,(IX+nn)
DDCBnnBC
|
| L |
RES L,0,(IX+nn)
DDCBnn85
|
RES L,1,(IX+nn)
DDCBnn8D
|
RES L,2,(IX+nn)
DDCBnn95
|
RES L,3,(IX+nn)
DDCBnn9D
|
RES L,4,(IX+nn)
DDCBnnA5
|
RES L,5,(IX+nn)
DDCBnnAD
|
RES L,6,(IX+nn)
DDCBnnB5
|
RES L,7,(IX+nn)
DDCBnnBD
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
6 - RES Reset bit in (IY+d) and copy into register r
Undocumented Reset bit in (IY+d) and copy into register r
There are a few undocumented instructions that performs an action and then copies the result into a register.
For example the official RES 0,(IY+nn) instruction resets bit 0 on a specific memory address,
however the undocumented RES B,0,(IY+nn)0xFDCBnn00 instruction does the same thing but then
copies the result into the B register.
\((IY+d)_b \longleftarrow 0 \\ r \longleftarrow (IY+d)\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 1 | 0 | b | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Bits
| Value | b |
| 0 | 000 |
| 1 | 001 |
| 2 | 010 |
| 3 | 011 |
| 4 | 100 |
| 5 | 101 |
| 6 | 110 |
| 7 | 111 |
Z is set if the specified bit in the source is 0, otherwise it is cleared.
The result is stored both in memory and the specified register.
r=%110 does exist, it is the official documented operation with no auto-copy to a register.
Opcode Matrix
| BIT 0 | BIT 1 | BIT 2 | BIT 3 | BIT 4 | BIT 5 | BIT 6 | BIT 7 |
|---|
| A |
RES A,0,(IY+nn)
FDCBnn87
|
RES A,1,(IY+nn)
FDCBnn8F
|
RES A,2,(IY+nn)
FDCBnn97
|
RES A,3,(IY+nn)
FDCBnn9F
|
RES A,4,(IY+nn)
FDCBnnA7
|
RES A,5,(IY+nn)
FDCBnnAF
|
RES A,6,(IY+nn)
FDCBnnB7
|
RES A,7,(IY+nn)
FDCBnnBF
|
| B |
RES B,0,(IY+nn)
FDCBnn80
|
RES B,1,(IY+nn)
FDCBnn88
|
RES B,2,(IY+nn)
FDCBnn90
|
RES B,3,(IY+nn)
FDCBnn98
|
RES B,4,(IY+nn)
FDCBnnA0
|
RES B,5,(IY+nn)
FDCBnnA8
|
RES B,6,(IY+nn)
FDCBnnB0
|
RES B,7,(IY+nn)
FDCBnnB8
|
| C |
RES C,0,(IY+nn)
FDCBnn81
|
RES C,1,(IY+nn)
FDCBnn89
|
RES C,2,(IY+nn)
FDCBnn91
|
RES C,3,(IY+nn)
FDCBnn99
|
RES C,4,(IY+nn)
FDCBnnA1
|
RES C,5,(IY+nn)
FDCBnnA9
|
RES C,6,(IY+nn)
FDCBnnB1
|
RES C,7,(IY+nn)
FDCBnnB9
|
| D |
RES D,0,(IY+nn)
FDCBnn82
|
RES D,1,(IY+nn)
FDCBnn8A
|
RES D,2,(IY+nn)
FDCBnn92
|
RES D,3,(IY+nn)
FDCBnn9A
|
RES D,4,(IY+nn)
FDCBnnA2
|
RES D,5,(IY+nn)
FDCBnnAA
|
RES D,6,(IY+nn)
FDCBnnB2
|
RES D,7,(IY+nn)
FDCBnnBA
|
| E |
RES E,0,(IY+nn)
FDCBnn83
|
RES E,1,(IY+nn)
FDCBnn8B
|
RES E,2,(IY+nn)
FDCBnn93
|
RES E,3,(IY+nn)
FDCBnn9B
|
RES E,4,(IY+nn)
FDCBnnA3
|
RES E,5,(IY+nn)
FDCBnnAB
|
RES E,6,(IY+nn)
FDCBnnB3
|
RES E,7,(IY+nn)
FDCBnnBB
|
| H |
RES H,0,(IY+nn)
FDCBnn84
|
RES H,1,(IY+nn)
FDCBnn8C
|
RES H,2,(IY+nn)
FDCBnn94
|
RES H,3,(IY+nn)
FDCBnn9C
|
RES H,4,(IY+nn)
FDCBnnA4
|
RES H,5,(IY+nn)
FDCBnnAC
|
RES H,6,(IY+nn)
FDCBnnB4
|
RES H,7,(IY+nn)
FDCBnnBC
|
| L |
RES L,0,(IY+nn)
FDCBnn85
|
RES L,1,(IY+nn)
FDCBnn8D
|
RES L,2,(IY+nn)
FDCBnn95
|
RES L,3,(IY+nn)
FDCBnn9D
|
RES L,4,(IY+nn)
FDCBnnA5
|
RES L,5,(IY+nn)
FDCBnnAD
|
RES L,6,(IY+nn)
FDCBnnB5
|
RES L,7,(IY+nn)
FDCBnnBD
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
7 - SET bit in (IX+d) and copy into register r
Undocumented SET bit in (IX+d) and copy into register r
There are a few undocumented instructions that performs an action and then copies the result into a register.
For example the official SET 0,(IX+nn) instruction sets bit 0 on a specific memory address,
however the undocumented SET B,0,(IX+nn)0xDDCBnn00 instruction does the same thing but then
copies the result into the B register.
\((IX+d)_b \longleftarrow 0 \\ r \longleftarrow (IX+d)\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 1 | 1 | b | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Bits
| Value | b |
| 0 | 000 |
| 1 | 001 |
| 2 | 010 |
| 3 | 011 |
| 4 | 100 |
| 5 | 101 |
| 6 | 110 |
| 7 | 111 |
Z is set if the specified bit in the source is 0, otherwise it is cleared.
The result is stored both in memory and the specified register.
r=%110 does exist, it is the official documented operation with no auto-copy to a register.
Opcode Matrix
| BIT 0 | BIT 1 | BIT 2 | BIT 3 | BIT 4 | BIT 5 | BIT 6 | BIT 7 |
|---|
| A |
SET A,0,(IX+nn)
DDCBnnC7
|
SET A,1,(IX+nn)
DDCBnnCF
|
SET A,2,(IX+nn)
DDCBnnD7
|
SET A,3,(IX+nn)
DDCBnnDF
|
SET A,4,(IX+nn)
DDCBnnE7
|
SET A,5,(IX+nn)
DDCBnnEF
|
SET A,6,(IX+nn)
DDCBnnF7
|
SET A,7,(IX+nn)
DDCBnnFF
|
| B |
SET B,0,(IX+nn)
DDCBnnC0
|
SET B,1,(IX+nn)
DDCBnnC8
|
SET B,2,(IX+nn)
DDCBnnD0
|
SET B,3,(IX+nn)
DDCBnnD8
|
SET B,4,(IX+nn)
DDCBnnE0
|
SET B,5,(IX+nn)
DDCBnnE8
|
SET B,6,(IX+nn)
DDCBnnF0
|
SET B,7,(IX+nn)
DDCBnnF8
|
| C |
SET C,0,(IX+nn)
DDCBnnC1
|
SET C,1,(IX+nn)
DDCBnnC9
|
SET C,2,(IX+nn)
DDCBnnD1
|
SET C,3,(IX+nn)
DDCBnnD9
|
SET C,4,(IX+nn)
DDCBnnE1
|
SET C,5,(IX+nn)
DDCBnnE9
|
SET C,6,(IX+nn)
DDCBnnF1
|
SET C,7,(IX+nn)
DDCBnnF9
|
| D |
SET D,0,(IX+nn)
DDCBnnC2
|
SET D,1,(IX+nn)
DDCBnnCA
|
SET D,2,(IX+nn)
DDCBnnD2
|
SET D,3,(IX+nn)
DDCBnnDA
|
SET D,4,(IX+nn)
DDCBnnE2
|
SET D,5,(IX+nn)
DDCBnnEA
|
SET D,6,(IX+nn)
DDCBnnF2
|
SET D,7,(IX+nn)
DDCBnnFA
|
| E |
SET E,0,(IX+nn)
DDCBnnC3
|
SET E,1,(IX+nn)
DDCBnnCB
|
SET E,2,(IX+nn)
DDCBnnD3
|
SET E,3,(IX+nn)
DDCBnnDB
|
SET E,4,(IX+nn)
DDCBnnE3
|
SET E,5,(IX+nn)
DDCBnnEB
|
SET E,6,(IX+nn)
DDCBnnF3
|
SET E,7,(IX+nn)
DDCBnnFB
|
| H |
SET H,0,(IX+nn)
DDCBnnC4
|
SET H,1,(IX+nn)
DDCBnnCC
|
SET H,2,(IX+nn)
DDCBnnD4
|
SET H,3,(IX+nn)
DDCBnnDC
|
SET H,4,(IX+nn)
DDCBnnE4
|
SET H,5,(IX+nn)
DDCBnnEC
|
SET H,6,(IX+nn)
DDCBnnF4
|
SET H,7,(IX+nn)
DDCBnnFC
|
| L |
SET L,0,(IX+nn)
DDCBnnC5
|
SET L,1,(IX+nn)
DDCBnnCD
|
SET L,2,(IX+nn)
DDCBnnD5
|
SET L,3,(IX+nn)
DDCBnnDD
|
SET L,4,(IX+nn)
DDCBnnE5
|
SET L,5,(IX+nn)
DDCBnnED
|
SET L,6,(IX+nn)
DDCBnnF5
|
SET L,7,(IX+nn)
DDCBnnFD
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |
8 - SET bit in (IY+d) and copy into register r
Undocumented SET bit in (IY+d) and copy into register r
There are a few undocumented instructions that performs an action and then copies the result into a register.
For example the official SET 0,(IY+nn) instruction sets bit 0 on a specific memory address,
however the undocumented SET B,0,(IY+nn)0xFDCBnn00 instruction does the same thing but then
copies the result into the B register.
\((IY+d)_b \longleftarrow 0 \\ r \longleftarrow (IY+d)\)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d |
| 1 | 1 | b | r |
Registers
| Register | r |
|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Bits
| Value | b |
| 0 | 000 |
| 1 | 001 |
| 2 | 010 |
| 3 | 011 |
| 4 | 100 |
| 5 | 101 |
| 6 | 110 |
| 7 | 111 |
Z is set if the specified bit in the source is 0, otherwise it is cleared.
The result is stored both in memory and the specified register.
r=%110 does exist, it is the official documented operation with no auto-copy to a register.
Opcode Matrix
| BIT 0 | BIT 1 | BIT 2 | BIT 3 | BIT 4 | BIT 5 | BIT 6 | BIT 7 |
|---|
| A |
SET A,0,(IY+nn)
FDCBnnC7
|
SET A,1,(IY+nn)
FDCBnnCF
|
SET A,2,(IY+nn)
FDCBnnD7
|
SET A,3,(IY+nn)
FDCBnnDF
|
SET A,4,(IY+nn)
FDCBnnE7
|
SET A,5,(IY+nn)
FDCBnnEF
|
SET A,6,(IY+nn)
FDCBnnF7
|
SET A,7,(IY+nn)
FDCBnnFF
|
| B |
SET B,0,(IY+nn)
FDCBnnC0
|
SET B,1,(IY+nn)
FDCBnnC8
|
SET B,2,(IY+nn)
FDCBnnD0
|
SET B,3,(IY+nn)
FDCBnnD8
|
SET B,4,(IY+nn)
FDCBnnE0
|
SET B,5,(IY+nn)
FDCBnnE8
|
SET B,6,(IY+nn)
FDCBnnF0
|
SET B,7,(IY+nn)
FDCBnnF8
|
| C |
SET C,0,(IY+nn)
FDCBnnC1
|
SET C,1,(IY+nn)
FDCBnnC9
|
SET C,2,(IY+nn)
FDCBnnD1
|
SET C,3,(IY+nn)
FDCBnnD9
|
SET C,4,(IY+nn)
FDCBnnE1
|
SET C,5,(IY+nn)
FDCBnnE9
|
SET C,6,(IY+nn)
FDCBnnF1
|
SET C,7,(IY+nn)
FDCBnnF9
|
| D |
SET D,0,(IY+nn)
FDCBnnC2
|
SET D,1,(IY+nn)
FDCBnnCA
|
SET D,2,(IY+nn)
FDCBnnD2
|
SET D,3,(IY+nn)
FDCBnnDA
|
SET D,4,(IY+nn)
FDCBnnE2
|
SET D,5,(IY+nn)
FDCBnnEA
|
SET D,6,(IY+nn)
FDCBnnF2
|
SET D,7,(IY+nn)
FDCBnnFA
|
| E |
SET E,0,(IY+nn)
FDCBnnC3
|
SET E,1,(IY+nn)
FDCBnnCB
|
SET E,2,(IY+nn)
FDCBnnD3
|
SET E,3,(IY+nn)
FDCBnnDB
|
SET E,4,(IY+nn)
FDCBnnE3
|
SET E,5,(IY+nn)
FDCBnnEB
|
SET E,6,(IY+nn)
FDCBnnF3
|
SET E,7,(IY+nn)
FDCBnnFB
|
| H |
SET H,0,(IY+nn)
FDCBnnC4
|
SET H,1,(IY+nn)
FDCBnnCC
|
SET H,2,(IY+nn)
FDCBnnD4
|
SET H,3,(IY+nn)
FDCBnnDC
|
SET H,4,(IY+nn)
FDCBnnE4
|
SET H,5,(IY+nn)
FDCBnnEC
|
SET H,6,(IY+nn)
FDCBnnF4
|
SET H,7,(IY+nn)
FDCBnnFC
|
| L |
SET L,0,(IY+nn)
FDCBnnC5
|
SET L,1,(IY+nn)
FDCBnnCD
|
SET L,2,(IY+nn)
FDCBnnD5
|
SET L,3,(IY+nn)
FDCBnnDD
|
SET L,4,(IY+nn)
FDCBnnE5
|
SET L,5,(IY+nn)
FDCBnnED
|
SET L,6,(IY+nn)
FDCBnnF5
|
SET L,7,(IY+nn)
FDCBnnFD
|
Opcode Matrix Legend
|
Instruction
Opcode hex
| | Undocumented |