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There are a few undocumented instructions that performs an action and then copies the result into a register.
For example the official RLC (IX+nn)0xDDCBnn06 instruction operates on a specific memory address,
however the undocumented RLC B,(IX+nn)0xDDCBnn00 instruction does the same thing but then
copies the result into the B register.
This instruction performs an RL (IX+dd) or RL (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RL r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 0 | r | |||
| RL r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 0 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
RL A,(IX+d)
DDCBnn17 |
RL B,(IX+d)
DDCBnn10 |
RL C,(IX+d)
DDCBnn11 |
RL D,(IX+d)
DDCBnn12 |
RL E,(IX+d)
DDCBnn13 |
RL H,(IX+d)
DDCBnn14 |
RL L,(IX+d)
DDCBnn15 |
| (IY+d) |
RL A,(IY+d)
FDCBnn17 |
RL B,(IY+d)
FDCBnn10 |
RL C,(IY+d)
FDCBnn11 |
RL D,(IY+d)
FDCBnn12 |
RL E,(IY+d)
FDCBnn13 |
RL H,(IY+d)
FDCBnn14 |
RL L,(IY+d)
FDCBnn15 |
|
Instruction
Opcode hex
| Undocumented |
This instruction performs an RLC (IX+dd) or RLC (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RLC r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 0 | r | |||
| RLC r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 0 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
RLC A,(IX+d)
DDCBnn07 |
RLC B,(IX+d)
DDCBnn00 |
RLC C,(IX+d)
DDCBnn01 |
RLC D,(IX+d)
DDCBnn02 |
RLC E,(IX+d)
DDCBnn03 |
RLC H,(IX+d)
DDCBnn04 |
RLC L,(IX+d)
DDCBnn05 |
| (IY+d) |
RLC A,(IY+d)
FDCBnn07 |
RLC B,(IY+d)
FDCBnn00 |
RLC C,(IY+d)
FDCBnn01 |
RLC D,(IY+d)
FDCBnn02 |
RLC E,(IY+d)
FDCBnn03 |
RLC H,(IY+d)
FDCBnn04 |
RLC L,(IY+d)
FDCBnn05 |
|
Instruction
Opcode hex
| Undocumented |
This instruction performs an RR (IX+dd) or RR (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RR r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 1 | r | |||
| RR r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 1 | 1 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
RR A,(IX+d)
DDCBnn1F |
RR B,(IX+d)
DDCBnn18 |
RR C,(IX+d)
DDCBnn19 |
RR D,(IX+d)
DDCBnn1A |
RR E,(IX+d)
DDCBnn1B |
RR H,(IX+d)
DDCBnn1C |
RR L,(IX+d)
DDCBnn1D |
| (IY+d) |
RR A,(IY+d)
FDCBnn1F |
RR B,(IY+d)
FDCBnn18 |
RR C,(IY+d)
FDCBnn19 |
RR D,(IY+d)
FDCBnn1A |
RR E,(IY+d)
FDCBnn1B |
RR H,(IY+d)
FDCBnn1C |
RR L,(IY+d)
FDCBnn1D |
|
Instruction
Opcode hex
| Undocumented |
This instruction performs an RRC (IX+dd) or RRC (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| RRC r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 1 | r | |||
| RRC r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 0 | 0 | 1 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
RRC A,(IX+d)
DDCBnn0F |
RRC B,(IX+d)
DDCBnn08 |
RRC C,(IX+d)
DDCBnn09 |
RRC D,(IX+d)
DDCBnn0A |
RRC E,(IX+d)
DDCBnn0B |
RRC H,(IX+d)
DDCBnn0C |
RRC L,(IX+d)
DDCBnn0D |
| (IY+d) |
RRC A,(IY+d)
FDCBnn0F |
RRC B,(IY+d)
FDCBnn08 |
RRC C,(IY+d)
FDCBnn09 |
RRC D,(IY+d)
FDCBnn0A |
RRC E,(IY+d)
FDCBnn0B |
RRC H,(IY+d)
FDCBnn0C |
RRC L,(IY+d)
FDCBnn0D |
|
Instruction
Opcode hex
| Undocumented |
This instruction performs an SLA (IX+dd) or SLA (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| SLA r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 0 | r | |||
| SLA r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 0 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
SLA A,(IX+d)
DDCBnn27 |
SLA B,(IX+d)
DDCBnn20 |
SLA C,(IX+d)
DDCBnn21 |
SLA D,(IX+d)
DDCBnn22 |
SLA E,(IX+d)
DDCBnn23 |
SLA H,(IX+d)
DDCBnn24 |
SLA L,(IX+d)
DDCBnn25 |
| (IY+d) |
SLA A,(IY+d)
FDCBnn27 |
SLA B,(IY+d)
FDCBnn20 |
SLA C,(IY+d)
FDCBnn21 |
SLA D,(IY+d)
FDCBnn22 |
SLA E,(IY+d)
FDCBnn23 |
SLA H,(IY+d)
FDCBnn24 |
SLA L,(IY+d)
FDCBnn25 |
|
Instruction
Opcode hex
| Undocumented |
This instruction performs an SLL (IX+dd) or SLL (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
Note: This is an undocumented extension to an undocumented instruction.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| SLL r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 1 | 0 | r | |||
| SLL r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 1 | 0 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
SLL A,(IX+d)
DDCBnn37 |
SLL B,(IX+d)
DDCBnn30 |
SLL C,(IX+d)
DDCBnn31 |
SLL D,(IX+d)
DDCBnn32 |
SLL E,(IX+d)
DDCBnn33 |
SLL H,(IX+d)
DDCBnn34 |
SLL L,(IX+d)
DDCBnn35 |
| (IY+d) |
SLL A,(IY+d)
FDCBnn37 |
SLL B,(IY+d)
FDCBnn30 |
SLL C,(IY+d)
FDCBnn31 |
SLL D,(IY+d)
FDCBnn32 |
SLL E,(IY+d)
FDCBnn33 |
SLL H,(IY+d)
FDCBnn34 |
SLL L,(IY+d)
FDCBnn35 |
|
Instruction
Opcode hex
| Undocumented |
This instruction performs an SRA (IX+dd) or SRA (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| SRA r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 1 | r | |||
| SRA r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 0 | 1 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
SRA A,(IX+d)
DDCBnn2F |
SRA B,(IX+d)
DDCBnn28 |
SRA C,(IX+d)
DDCBnn29 |
SRA D,(IX+d)
DDCBnn2A |
SRA E,(IX+d)
DDCBnn2B |
SRA H,(IX+d)
DDCBnn2C |
SRA L,(IX+d)
DDCBnn2D |
| (IY+d) |
SRA A,(IY+d)
FDCBnn2F |
SRA B,(IY+d)
FDCBnn28 |
SRA C,(IY+d)
FDCBnn29 |
SRA D,(IY+d)
FDCBnn2A |
SRA E,(IY+d)
FDCBnn2B |
SRA H,(IY+d)
FDCBnn2C |
SRA L,(IY+d)
FDCBnn2D |
|
Instruction
Opcode hex
| Undocumented |
This instruction performs an SRL (IX+dd) or SRL (IX+dd) operation but then also stores
the result in a register as well as in the memory location.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| SRL r,(IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 1 | 1 | r | |||
| SRL r,(IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 0 | 0 | 1 | 1 | 1 | r | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
Note: r=%110 does exist. It doesn't do a copy into a register as it's the existing official, documented instruction.
| A | B | C | D | E | H | L | |
|---|---|---|---|---|---|---|---|
| (IX+d) |
SRL A,(IX+d)
DDCBnn3F |
SRL B,(IX+d)
DDCBnn38 |
SRL C,(IX+d)
DDCBnn39 |
SRL D,(IX+d)
DDCBnn3A |
SRL E,(IX+d)
DDCBnn3B |
SRL H,(IX+d)
DDCBnn3C |
SRL L,(IX+d)
DDCBnn3D |
| (IY+d) |
SRL A,(IY+d)
FDCBnn3F |
SRL B,(IY+d)
FDCBnn38 |
SRL C,(IY+d)
FDCBnn39 |
SRL D,(IY+d)
FDCBnn3A |
SRL E,(IY+d)
FDCBnn3B |
SRL H,(IY+d)
FDCBnn3C |
SRL L,(IY+d)
FDCBnn3D |
|
Instruction
Opcode hex
| Undocumented |