6502 Microprocessor

The 6502 8 bit Microprocessor

This is the classic 6502 Microprocessor. Originally produced by MOS in 1974, it is now produced by WDC (Western Design Center).

Pin descriptions

Pin Name Description
A0…A15 Address Bus The sixteen bit Address Bus formed by A0-A15, address memory and I/O registers that exchange data on the Data Bus. The address lines can be set to the high impedance state by the Bus Enable (BE) signal.
BE Bus Enable The Bus Enable (BE) input signal provides external control of the Address, Data and the RWB buffers. When Bus Enable is high, the Address, Data and RWB buffers are active. When BE is low, these buffers are set to the high impedance status. Bus Enable is an asynchronous signal.
D0…D7 Data Bus These lines may be set to the high impedance state by the Bus Enable (BE) signal.
IRQ Interrupt Request The processor initiates it's interrupt sequence when the IRQ line is pulled low. The IRQ signal should be held low until the interrupt handler clears the interrupt request source.
ML Memory Lock The Memory Lock (ML) output may be used to ensure the integrity of Read-Modify-Write instructions in a multiprocessor system. Memory Lock indicates the need to defer arbitration of the bus cycle when ML is low. Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory referencing instructions.
NMI Non-Maskable Interrupt A negative transition on the Non-Maskable Interrupt (NMI) input initiates an interrupt sequence after the current instruction is completed. Since NMI is an edge-sensitive input, an interrupt will occur if there is a negative transition while servicing a previous interrupt. Also, after the edge interrupt occurs no further interrupts will occur if NMI remains low.
NC No Connection Not connected internally. It should not be connected externally
2 (OUT)
1 (OUT)
Phase 2
Phase 2 Out
Phase 1 Out
Phase2 or ∅2 is the system clock input. ∅2 (Out) is generated from the ∅2 input. ∅1 (Out) is the inverted ∅2 signal.
R/W Read/Write The R/W signal is used to control data transfer. When it's in the high state the processor is reading memory. When it's in the low state the Data Bus contains valid data to be written to the memory address. The R/W signal is set to a high impedance state wheh Bus Enable is low.
RDY Ready A low signal on RDY will halt the processor in its current state. Returning to high signal will restart the processor on the next PHI2 negative transition. The WAI instruction (65C02 & later) will pull RDY low. If RDY is not used a pull-up resistor is recommended as newer processors no longer have an active pull-up.
RES Reset Initialise the microprocessor. The RES pin must be held low for at least 2 clock cycles after VDD reaches operating voltage. Ready (RDY) has no effect whilst RES is low. When a positive edge is detected on RES the processor will begin a reset sequence which is 7 cycles long.
SO Set Overflow A negative transition on the SO pin sets the overflow bit in the status register.
SYNC Synchronize with OpCode fetch The SYNC line is high when the processor is reading an instruction from memory (not whilst reading data). If the RDY line is pulled low during the same clock cycle as SYNC is high the processor will stop & remain stopped until RDY goes high. This can be used to implement hardware single instruction execution.
Power Positive power supply voltage. Some old data sheets shows this as VCC
VSS Ground System logic ground
VP Vector Pull The Vector Pull (VP) output indicates that a vector location is being addressed during an interrupt sequence.

Last modified October 21, 2021: Add resources sections (5d6dbeb)