The DS1691A/DS3691 are low power Schottky TTL line drivers designed to meet the requirements of EIA standards RS-422 and RS-423. They feature 4 buffered outputs with high source and sink current capability with internal short circuit protection. A mode control input provides a choice of operation either as 4 single-ended line drivers or 2 differential line drivers. A rise time control pin allows the use of an external capacitor to slow the rise time for suppression of near end crosstalk to other receivers in the cable. Rise time capacitors are primarily intended for waveshaping output signals in the single-ended driver mode. Multipoint applications in differential mode with waveshaping capacitors is not allowed.

With the mode select pin low, the DS1691A/DS3691 are dual-differential line drivers with TRI-STATE outputs. They feature ±10V output common-mode range in TRI-STATE mode and 0V output unbalance when operated with ±5V supply.

MCS6522 VERSATILE INTERFACE ADAPTER

DESCRIPTION

The MCS6522 Versatile Interface Adapter (VIA) provides all of the capability of the MCS6520. In addition, this device contains a pair of very powerful interval timers, a serial-to-parallel/ parallel-to-serial shift register and input data latching on the peripheral ports. Expanded handshaking capability allows control of bi-directional data transfers between VIA's in multiple processor systems.

Control of peripheral devices is handled primarily through two 8-bit bi-directional ports. Each of these lines can be programmed to act as either an input or an output. Also, several peripheral I/O lines can be controlled directly from the interval timers for generating programmable-frequency square waves and for counting externally generated pulses. To facilitate control of the many powerful features of this chip, the internal registers have been organized into an interrupt flag register, an interrupt enable register and a pair of function control registers.

• Very powerful expansion of basic MCS6520 capability.
• N channel, depletion load technology, single +5V supply.
• Completely static and TTL compatible.
• CMOS compatible peripheral control lines.
• Expanded "handshake" capability allows very positive control of data transfers between processor and peripheral devices.

PROCESSOR INTERFACE

This section contains a description of the buses and control lines which are used to interface the MCS6522 to the system processor. AC and DC parameters associated with this interface are specified on pages 21 through 24 of this document.

PHASE TWO CLOCK (02)

Data transfers between the MCS6522 and the system processor take place only while the Phase Two Clock is high. In addition, 02 acts as the time base for the various timers, shift registers, etc. on the chip.

CHIP SELECT LINES (CS₁, CS₂)

The two chip select inputs are normally connected to processor address lines either directly or through decoding. The selected MCS6522 register will be accessed when CS₁ is high and CS₂ is low.

REGISTER SELECT LINES (RSO, RSI, RS2, RS3)

The four Register select lines are normally connected to the processor address bus lines to allow the processor to select the internal MCS6522 register which is to be accessed. The sixteen possible combinations access the registers as follows:

READ/WRITE LINE (R/W)

The direction of data transfers between the MCS6522 and the system processor is controlled by the R/W line. If R/W is low, data will be transferred out of the processor into the selected MCS6522 register (write operation). If R/W is high and the chip is selected, data will be transferred out of the MCS6522 (read operation).

DATA BUS (D₀ - D₇)

The 8 bi-directional data bus lines are used to transfer data between the MCS6522 and the system processor. The internal drivers will remain in the high-impedance state except when the chip is selected (CS₁ = 1, CS₂ = 0), R/W is high and the Phase Two Clock is high. At this time, the contents of the selected register are placed on the data bus. When the chip is selected, with R/W low and ∅₂ = 1, the data on the data bus will be transferred into the selected MCS6522 register.

RESET (RES)

The Reset input clears all internal registers to logic 0 (except Tl, T2 and SR). This places all peripheral interface lines in the input state, disables the timers, shift register, etc. and disables interrupting from the chip.

INTERRUPT REQUEST (IRQ)

The Interrupt Request output goes low whenever an internal interrupt flag is set and the corresponding interrupt enable bit is a logic 1. This output is "open-drain" to allow the interrupt request signal to be "wire-or'ed" with other equivalent signals in the system.

PERIPHERAL INTERFACE

This section contains a brief description of the buses and control lines which are used to drive peripheral devices under control of the internal MCS6522 registers.

PERIPHERAL A PORT (PA₀ - PA₇)

The Peripheral A port consists of 8 lines which can be individually programmed to act as an input or an output under control of a Data Direction Register. The polarity of output pins is controlled by an Output Register and input data can be latched into an internal register under control of the CA₁ line. All of these modes of operation are controlled by the system processor through the internal control registers. These lines represent one standard TTL load in the input mode and will drive one standard TTL load in the output mode.

PERIPHERAL A CONTROL LINES (CA₁, CA₂)

The two peripheral A control lines act as interrupt inputs or as handshake outputs. Each line controls an internal interrupt flag with a corresponding interrupt enable bit. In addition, CA₁ controls the latching of data on Peripheral A Port input lines. The various modes of operation are controlled by the system processor through the internal control registers. CA₁ is a high-impedance input only while CA₂ represents one standard TTL load in the input mode. CA₂ will drive one standard TTL load in the output mode.

PERIPHERAL B PORT (PB₀ - PB₇)

The Peripheral B port consists of 8 bi-directional lines which are controlled by an output register and a data direction register in much the same manner as the PA port. In addition, the polarity of the PB₇ output signal can be controlled by one of the interval timers while the second timer can be programmed to count pulses on the PB₆ pin. These lines represent one standard TTL load in the input mode and will drive one standard TTL load in the output mode. In addition, they are capable of sourcing 30 ma at 1.5 VDC in the output mode to allow the outputs to directly drive Darlington transistor switches.

PERIPHERAL B CONTROL LINES (CB₁, CB₂)

The Peripheral B control lines act as interrupt inputs or as handshake outputs. As with CA₁ and CA₂, each line controls an interrupt flag with a corresponding interrupt enable bit. In addition, these lines act as a serial port under control of the Shift Register. These lines represent one standard TTL load in the input mode and will drive one standard TTL load in the output mode. In addition, they are capable of sourcing 1.0 ma at 1.5 VDC in the output mode to allow the outputs to directly drive Darlington transistor switches.

MCS6522 OPERATION

This section contains a discussion of the various blocks of logic shown in Figure 1. In addition, the internal operation of the MCS6522 is described in detail.

DATA BUS BUFFERS (DB), PERIPHERAL A BUFFERS (PA), PERIPHERAL B BUFFERS (PB)

The characteristics of the buffers which provide the required voltage and current drive capability were discussed in the previous section. -AC and DC parameters for these buffers are specified on pages 21 through 24 of this document.

CHIP ACCESS CONTROL

The Chip Access Control contains the necessary logic to detect the chip select condition and to decode the Register Select inputs to allow accessing the desired internal register. In addition, the R/W and ∅₂ signals are utilized to control the direction and timing of data transfers. When writing into the MCS6522, data is first latched into a date, input register during ∅₂. Data is then transferred into the desired internal register during ∅₂ CS. This allows the peripheral I/O line to change without "glitching." When the processor reads the MCS6522, data is transferred from the desired internal register directly onto the Data Bus during ∅₂.

PORT A REGISTERS, PORT B REGISTERS

Three registers are used in accessing each of the 8-bit peripheral, ports. Each port has a Data Direction Register (DDRA, DDRB) for specifying whether the peripheral pins are to act as inputs or outputs. A 0 in a bit of the Data Direction Register causes the corresponding peripheral pin to act as an input. A 1 causes the pin to act as an output.

Each peripheral pin is also controlled by a bit in the Output Register (ORA, ORB) and an Input Register (IRA, IRB). When the pin is programmed to act as an output, the voltage on the pin is controlled by the corresponding bit of the Output Register. A 1 in the Output Register causes the pin to go high, and a 0 causes the pin to go low. Data can be written into Output Register bits corresponding to pins which are programmed to act as inputs; however, the pin will be unaffected.

Reading a peripheral port causes the contents of the Input Register (IRA, IRB) to be transferred onto the Data Bus. With input latching disabled, IRA will always reflect the data on the PA pins. With input latching enabled, IRA will reflect the contents of the Port A prior to setting the CA1 Interrupt Flag (IFRl) by an active transition on CA₁.

The IRB register operates in a similar manner. However, for output pins, the corresponding IRB bit will reflect the contents of the Output Register bit instead of the actual pin. This allows proper data to be read into the processor if the output pin is not allowed to go to full voltage. With input latching enabled on Port B, setting CB₁ interrupt flag will cause IRB to latch this combination of input data and ORB data until the interrupt flag is cleared.

HANDSHAKE CONTROL

The MCS6522 allows very positive control of data transfers between the system processor and peripheral devices through the operation of "handshake" lines. Port A lines (CA1, CA2) handshake data on both a read and a write operation while the Port B lines (CB1, CB2) handshake on a write operation only.

Read Handshake

Positive control of data transfers from peripheral devices into the system processor can be accomplished very effectively using "Read" handshaking. In this case, the peripheral device must generate "Data Ready" to signal the processor that valid data is present on the peripheral port. This signal normally interrupts the processor, which then reads the data, causing generation of a "Data Taken" signal. The peripheral device responds by making new data available. This process continues until the data transfer is complete.

In the MCS6522, automatic "Read" handshaking is possible on the Peripheral A port only. The CAl interrupt input pin accepts the "Data Ready" signal and CA2 generates the "Data Taken" signal. The Data Ready signal will set an internal flag which may interrupt the processor or which can be polled under software control. The Data Taken signal can be either a pulse or a DC level which is set low by the system processor and is cleared by the Data Ready signal. These options are shown in Figure 3 which illustrates the normal Read Handshaking sequence.

Write Handshake

The sequence of operations which allows handshaking data from the system processor to a peripheral device is very similar to that described in Section A for Read Handshaking. However, for "Write" handshaking, the processor must generate the "Data Ready" signal (through the MCS6522) and the peripheral device must respond with the "Data Taken" signal. This can be accomplished on both the PA port and the PB port on the MCS6522. CA₂ or CB₂ acts as a Data Ready output in either the DC level or pulse mode and CA₁ or CB₁ accepts the "Data Taken" signal from the peripheral device, setting the interrupt flag and clearing the "Data Ready" output. This sequence is shown in Figure 4.

6560/6561 VIDEO INTERFACE CHIP

GENERAL DESCRIPTION

The 6560 Video Interface Chip (VIC) is designed for color video graphics applications such as low cost CRT terminals, biomedical monitors, control system displays and arcade or home video games.

It provides all of the circuitry necessary for generating color programmable character graphics with high screen resolution. VIC also incorporates sound effects and A/D converters for use in a video game environment.

FEATURES

• Fully expandable system with a 16K byte address space
• System uses industry standard 8 bit wide ROMS and 4 bit wide RAMS
• Mask programmable sync, generation, NTSC-6560, PAL-6561
• On-chip color generation (16 colors)
• Up to 600 independently programmable and movable background locations on a standard TV
• Screen centering capability
• Screen grid size up to 192 Horizontal by 200 Vertical dots
• Two selectable graphic character sizes
• On-chip sound system including:
  • Three independent, programmable tone generators
  • White noise generator
  • Amplitude modulator
• Two on-chip 8 bit AID converters
• On-chip DMA and address generation
• No CPU wait states or screen hash during screen refresh
• Interlaced/Non-interlaced switch
• 16 addressable control registers
• Light gun/pen for target games
• 2 modes of color operation

Variants

THEORY OF OPERATION

In order to produce programmable color characters, VIC accesses external memory which can be divided into three areas: character pointers, display characters and color pointers. The character pointer area is a block of bytes in RAM (typically 506 bytes called the Video Matrix) in which each byte points to a particular character to be displayed. The character area consists of a set of 8 or 16 byte blocks (usually called cells) which contain the actual dot patterns to be displayed. These character cells can be located in either RAM or ROM depending on how the objects are to be displayed or moved on the screen. The color pointer area is a block of nybbles in RAM (typically 506-4 bit nybbles called the Color Matrix). The 4 bit color pointers are used to define the color of any character which is to be displayed and to select one of the two color modes.

It is the task of an external microprocessor to organize the Video Matrix, Color Matrix and Character Cells into the proper format to display the data desired on-screen.

To understand the operation of VIC more completely, consider the diagram shown in Figure 1. This is a typical Video Matrix, in which 22 characters horizontally by 23 characters vertically are to be displayed, yielding a total of 506 character display locations, with a screen resolution of 176 horizontal by 184 vertical dots. Each one of these character display locations has a corresponding character pointer, or index, which specifies (points at) a character to be displayed in that particular location. In the example shown, rectangle (B,15) has a character index of 2B. This means character number 2B is to be displayed in that rectangle. VIC will fetch the character index value 2B and perform an address computation to locate the desired character to be displayed. The computation is quite simple. If 8 x 8 character cells are selected, the index is left shifted 3 times (multiply by 8) and the starting address of the character cells, found in VIC Control Register CR5, is added to the left shifted value. In this case, the character cell starting address is 3400 (in HEX) which is added to the left shifted value of the character index to yield the actual character location in memory of 3558 (in HEX). Note here that the actual character displayed is an eight dot by eight dot matrix which can be stored in either ROM or RAM. Also, the number of times that any particular character can be displayed is unlimited. By using the same character index (2B for example) elsewhere on the grid, the character data will be displayed again. Alternately, through the use of a simple software driver, VIC can be used as a bit mapped display system provided enough RAM is available (approximately 4K bytes of cell RAM).

REGISTER DESCRIPTION

There are sixteen eight-bit control registers within the 6560 which enable the microprocessor to control all the operating modes of VIC.

EXPLANATION OF CONTROL REGISTER FUNCTIONS

COLOR OPERATING MODES

VIC incorporates two modes of color operation. HI-RES (high resolution) mode and Multicolor mode. Basically, the operating mode affects how the Character Cell information will be translated into dots on the TV screen. The operating mode is determined by the MSB of the color pointer associated with each character location in the Video Matrix. If the MSB of a character’s color pointer is zero, then that character will be displayed in HI-RES mode. Alternately, if the MSB is one, the character will be displayed in Multicolor mode

With HI-RES mode selected, there is a one-to-one correspondence between Character Cell bits and the dots displayed on-screen. That is, all one bits of a character will be displayed in one color, and all zero bits in another color. The foreground color of the character is specified by the remaining 3 bits of the character’s color pointer, while the character’s background color is specified by Register F (CR_F).

With Multicolor mode selected, each TWO bits of a character cell correspond to ONE dot on-screen and the color of that dot is determined by the two-bit code. Unlike HI-RES mode, in which only two colors can be displayed in a single character, Multicolor mode allows four colors per character; however, since two bits of cell data now correspond to a single dot on-screen, the horizontal resolution is half that of the HI-RES mode. That is, each 8x8 Character Cell in memory maps onto an 8x4 character on-screen (8 lines of 4 dots each). Note that the amount of memory required for these 8x4 Multicolor characters is the same as that for 8x8 HI-RES characters, the data is simply mapped differently on-screen.

In Multicolor mode, the two bits which make up a dot select one of four colors for that dot. The four codes created by these two bits tell VIC where to find the color information for the dot. The color of the dot can be either the Background color (in C R F), the Exterior Border color in (CRF), the Auxiliary color (in C R E) or the Foreground color (bits 0 thru 2 of the character’s color pointer).

The Multicolor mode color select codes are:

Note that the two-bit code is NOT itself a color code, rather it is a pointer to four different color codes, allowing greater color flexibility, as each code pointed to has either 3 or 4-bit resolution

6560 PIN SIGNAL DESCRIPTION

• Address Bus— Pins 21 thru 34

The 14 bit address bus (A₀ thru A₁₃) is bidirectional. During P∅₂ = 1, the address pins are in the input mode. In this mode the microprocessor can access any of the sixteen VIC Control Registers. The high order pins of the Address Bus (A₈ thru A₁₃) act as Chip Select pins in this input mode. A true chip select condition occurs when A₁₃ = A₁₁ = A₁₀ = A₉ = A₈ = 0 and A₁₂ = 1, which equates to a VIC chip select address of 1000 in HEX. The lower order 4 bits of the address bus (A₀ thru A₃) are used as the control register select portion of the input address

During P∅₁ = 1, the VIC address pins will be in the output mode if data (either Character Pointer or Character Cell) is to be fetched. In this mode, VIC will put out the address of the memory location to be fetched. The address from VIC will be valid 50ns after the rising edge of P∅₁ and remain valid until the rising edge of P∅₂.

• Read/Write— Pin 4

This signal is an input only on the 6560 and controls the flow of data between VIC and the microprocessor. When the R/W signal is low and the VIC chip select conditions have been satisfied, the microprocessor can write data into the selected VIC Control Register. If the R/W signal is high and the chip select conditions have been met, the microprocessor can read data from the selected VIC Control Register

It is important to note that all VIC/microprocessor data transfers can only occur when P∅₂=1. During P∅₁ the VIC will be fetching data from memory for display and the R/W signal must be held high to ensure that VIC will not write into any memory location

Data Bus— Pins 5 thru 16

The 12 bit data bus of the 6560, DB0 thru DB11f is divided into two sections. The lower order eight bits, DB0 thru DB7, are used both to interface to the microprocessor and fetch data needed for display, while the higher order 4 bits are used exclusively for retrieving color and mode information. The operation of the lower order eight bits (DB0 thru DB7) can also be separated into two categories: microprocessor interface and video data interface. During P 0 2=1, DB7 thru DB0 are used exclusively for data transmission between the microprocessor and VIC. During P 0 1 = 1, DB7 thru DB0 are used for fetching display data.

CLOCKS

Master Oscillator Clock Inputs— 0 A and 0 2, Pins 39 and 38

The 6560 requires a 14.31818 MHz (NTSC), TWO Phase Clock. The clock signals must be five (5) volts and non-overlapping. The 6561 requires a 4.436187 M H z clock for PAL standard

System Clocks— P 0 1 and P 0 2, Pins 35 and 36

These clocks are the master timing generator for the VIC System. They are five volt, nonoverlapping 1.02 MH z clocks capable of driving the capacitance of the 6512 microprocessor.

Memory Clock— 0 M (Option), Pin 37

This is a single phase 2.04 MHz clock used when memories in the VIC System require a strobe after the address bus is valid.

Analog to Digital Converters— POTX and POTY, Pins 17 and 18

These input pins are used to convert potentiometer position into a microprocessor readable 8 bit HEX number. This is accomplished by a simple RC time constant integration technique. The potentiometer is used to charge an external capacitor tied to the pot pin. Refer to application note No.1 (insert).

Composite Sound— Pin 19

This pin provides the output of the sound synthesizer portion of the 6560 shown in the VIC Block Diagram. It is a high impedance output (approximately 1Kfi) and must be buffered and amplified externally to drive a speaker

Composite Sync and Luminance— Pin 3

This pin is an open drain output which provides all the necessary video synchronization and luminance information required by a standard television. Refer to application note No. 1 (insert).

Composite Color— Pin 2

This signal provides the necessary color information required by a standard television to receive a full color picture. The composite color pin is a high impedance output buffer which provides the reference burst signal plus the color encoded phase and amplitude information at the proper 3.579545 M H z frequency. Refer to application note No. 1 (insert).

Reset— (Option), Pin 37

This input signal is used to synchronize the horizontal and vertical sync counter to an external signal.

Bus Available— (Option), Pin 37

This output signal indicates the state of VIC with respect to the video memory fetch. The pin will go low 2 ^sec. before VIC performs any memory access and will remain low until the entire screen has been refreshed.

Light Gun/Pen— (Option), Pin 37

This input signal causes the current dot position being scanned onto the screen to be latched into control registers 6 and 7, upon a negative going edge. This pin would be used in conjunction with a photo detector for use in a “target shoot” type game or for light pen applications. Refer to application note No. 1 (insert).

AVAILABLE AUXILIARY/BACKGROUND COLORS

AVAILABLE BORDER/CHACTER COLORS

6567 Video Interface Chip

General Description:

The 6567 Video Interface Chip (VIC II) is a multi-purpose video controller for use in both computer video terminals and video game applications. The color video display is 25 rows of 40 characters each with additional features including horizontal and vertical scroll, bit map graphics and movable image blocks (MIBS).

Features

• Mask programmable sync, generation, NTSC - 6567, PAL - 6569, PAL-N-6572, PAL-M-6573.
• 47 Addressable control registers.
• Fully expandable system with up to 16K byte display memory.
• On chip color generation (16 colors)
• Up to eight independent movable image blocks (MIBS).
• Light gun/pen for target games.

(Multiplexed addresses in parentheses)

Variants

CHARACTER DISPLAY MODE

In the character display mode, the 6567 fetches CHARACTER POINTERS from the VIDEO MATRIX area of memory and translates the pointers to character dot addresses in the 2,048 byte CHARACTER BASE area of memory. The video matrix is comprised of 1,000 consecutive locations in memory which each contain an eight bit character pointer. The location of the video matrix within memory is defined by bits VM13-VM10 in register 24 (0x18) which are used as the 4 MSB of the video matrix address. The lower order 10 bits are provided by an internal couiter (VC9-VC0) which steps through the 1000 character locations. Note that the 6567 provides only 14 address outputs so additional system hardware may be required for complete system memory decodes.

The eight bit character pointer permits 256 different .character definitions to be available simultaneously. Each character is an 8x8 matrix of dots stored in the character base as eight consecutive bytes. The location of the character base is defined by bits CB13-CB11 in register 24 (0x18) which are used for the 3 most significant bits (MSB) of the character base address. The 11 lower order addresses are formed by the 8 bit character pointer from the video matrix (D7-D0) which selects a particluar character, and a 3 bit raster counter (RC2-RC0) which selects one of the eight character bytes. The resulting characters are formated as 25 rows of 40 characters each. In addition to the 8 bit character pointer, a 4-bit COLOR NYBBLE is associated with each video matrix location (the video matrix memory is 12 bits wide) which selects one of sixteen colors for each character.

EXTENDED COLOR CHARACTER MODE

The extended color mode allows the selection of individual background colors for each character region while maintaining the normal 8 x 8 character resolution. This mode is selected by setting the-BCM bit of register 17 (0x11) to "1M. The character dot data is displayed similar to the standard mode except the 2 MSB of the character pointer are used to select the background color for each character region.

Since the two MSB of the character pointers are used for color information, only 64 different character definitions are available. The 8562 forces CB10 and QB9 to "0" regardless of the original pointer values, so that only the first 64 character definitions are accessed. In extended color mode, each character can select one of sixteen individually defined foreground colors and one of the four available background colors.

EXTENDED COLOR MODE AND MULTI-COLOR MODE CAN NOT BE ENABLED SIMULTANEOUSLY.

BIT MAP MODE

In bit map mode, the 6567 fetches data from memory to create a one-to-one correspondence between each displayed dot and memory bit. The bit map mode- provides a screen resolution of 320H x ' 200V individually controllable display dots. Bit map mode is selected by setting the BMM bit in register 17 (0x11) to a ”1". The VIDEO MATRIX is accessed as in character mode, but the video matrix data is interpreted as color data rather than as character pointers. The VIDEO MATRIX COUNTER is also used to create the address to fetch the dot data for display from the 3,000 byte DISPLAY BASE. The display data address is formed as follows:

VM_x denotes the video matrix counter outputs, RC_x denotes the 3 bit raster line counter and CB₁₃ is from register 24 (0x18). The raster counter increments once each horizontal video line (raster line) and the video matrix counter increments once every eight lines. This address sequence causes each 8x8 dot block of the video display to reflect eight sequential memory locations.

STANDARD BIT MAP MODE

In the standard bit map mode, color information is derived only from the data stored in the video matrix (the color nybble is disregarded).

These 8 bits are divided into two 4-bit nybbles, allowing two colors to be selected independently in each 8x8 dot block.

When a bit in the display memory is a "0", the color of the output dot is set by the least significant (lower) nybble (LSN).

Similarly, a display memory bit of "1" selects the output color specified by the MSN (upper nybble).

MULTI-COLOR BIT MAP MODE

Multi-colored bit map mode is selected by setting the MCM bit in register 22 (0x16) to a "1" in conjunction with the B W bit. Multi-color mode utilizes the same memory addressing sequence as standard bit map mode, but interpretes the display dot data differently.

Note that the color nybble (DB11-DB8) IS used for the multi-color bit map mode. As in character multi-color mode, the horizontal dot size is doubled since two bits are required for color selection, resulting in a screen resolution of 160H x 200V. Utilizing multi-color bit map mode, three independently selected colors can be displayed in each 8 x 8 block in addition to the background color.

MOVABLE IMAGE BLOCKS

The movable image block (MIB) is a special type of display image which can be displayed at any screen position without the 8x8 dot block constraints inherent in character and bit map modes. Up to 8 unique MIBs can be displayed simultaneously, each defined by 63 bytes in memory displayed as a 24x21 dot array (shown below). A number of special features make MIBs especially suited for video graphics and game applicatons.

MIB ENABLE

Each MIB can be selectively enabled for display by setting its corresponding enable bit (MnE) to "1” in register 21 (0x15).

If the MnE bit is "0", the MIB will not be displayed.

MIB POSITION

Each MIB is positioned via its X and Y position register (see register map 1.3) within 512 horizontal and 256 vertical positions. The position of a MIB is specified by the upper-left corner of the array.

X locations 23 to 347 (0x17-0x157) and Y locations 50 to 249 (0x32-0xF9) are visible.

Since not all available MIB positions are entirely visible on the screen, MIBs may be moved smoothly on and off the display screen

MIB COLOR

A separate 4-bit register is associated with each MIB to specify the MIB color. There are two MIB color modes.

STANDARD MIB COLOR

In the standard mode, a "0" bit of MIB data allows any background, character or bit map data to show through (transparent) and a "1" bit is displayed £s the MIB color determined by the corresponding MIB Color register.

MULTI-COLOR MIB

Each MIB can be individually specified to be multi-color via MnMC bits in the MIB multi-color register 28 (0x1C). When the MnMC bit is H1H, the corresponding MIB is displayed in the multi-color mode. In the multi-color mode, the MIB data is interpreted in pairs as in the other multi-color modes.

Since two bits of data are required for each color, the resolution of the MIB is reduced to 12 H x 21 V. Each horizontal dot is expanded to twice the standard size so that the size of the overall MIB does not change. Up to 3 colors can be displayed in each MIB (in addition to transparent), but the two colors specified by the MIB multi-color registers are shared among all 8 MIBs.

MIB MAGNIFICATION

Each MIB can be independently expanded (2X) in both the horizontal and vertical directions.

Two registers contain the control bits (MiXE,MnYE) for the magnification control:

No increase in resolution is realized by expanding the MIBs.

The same 24x21 array (or 12x21 if multi-colored) is displayed except but the size of each dot is doubled in the desired direction (up to 4X standard dot dimension if a MIB is both multi-colored and expanded).

MIB PRIORITY

The priority of each MIB may be individually controlled with respect to the other displayed information (from character or bit map modes).

The priority of each MIB is set by the corresponding bit (MnDP) of register 27 (SIB):

MIB data bits of "0" always permit any other information to be displayed (i.e. MIB transparent sections).

The MIBs have a fixed priority with respect to each other, with MIB 0 having the highest priority (in front) and MIB 7 the lowest (behind).

When MIB data (except transparent data) of two MIBs are co-incident, the data from the lower number MIB will be displayed.

COLLISION DETECTION

Two types of MIB collision (co-incidence) are detected, MIB to MIB collision and MIB to display data collision.

MIB TO MIB COLLISION

A collision between two MIBs occurs when non-transparent output data of two MIBs are co-incident. Co-incidence of MIB transparent areas will not generate a collision.

When a collision occurs, the MIB bits (ttiM) in the MIB-MIB COLLISION register 30 (0x1E) will be set to "1" for each colliding MIB.

The collision bits remain set until a read of the collision register, when they are automatically cleared.

MIBs collisions are detected even if off-screen, behind the border.

MIB TO DATA COLLISION

A second register, MIB-DATA COLLISION register 31 (0x1F) also contains a bit (MiD) for each MIB which is set to "1" when both the MIB and display data are co-incident. Again, the co-incidence of MIB transparent data and/or display background does not generate a collision.

For special applications, the display data from the 0-1 multicolor bit pair also does not cause a collision. This feature permits their use as background display data without interfering with true MIB collisions.

A MIB-DATA collision can occur off-screen in the horizontal direction if display data has been scrolled to an off-screen position (see scrolling).

The MIB-DATA COLLISION register also automatically clears when read

MIB COLLISION INTERRUPTS

The collision interrupt latches are set whenever the first bit of either register is set to "1". Once any collision bit within a register is set high, subsequent collisions will not set the interrupt latch until that collision register has been cleared to all "0"s by a read.

MIB MEMORY ACCESS

The data for each MIB is stored in 63 consecutive bytes of memory. Each block of MIB data is defined by a MIB pointer, located at the end of the VIDEO MATRIX.

Since only 1,000 bytes of the video matrix are used in the normal display modes video matrix locations 1016-1023 (0x3F8-0x3FF) are used for MIB pointers 0-7 respectively.

The eight bit MIB pointer from the video matrix together with the six bits from the MIB byte counter to count through the 63 bytes define the entire 14-bit address field.

The MP_x are the MIB pointer bits from the video matrix and MC_x are the internally generated MIB counter bits. The MIB pointers are read from the video matrix at the end of every raster line.

When the Y position register of a MIB matches the current raster line count, the actual fetches of MIB data begin. Internal counters automatically step through the 63 bytes of MIB data, displaying three bytes on each raster line.

OTHER FEATURES

SCREEN BLANKING

The display screen may be blanked by setting the BLNK bit in register 17 (0x11) to a H1H. when the screen in blanked, the entire screen displays the exterior color specified by register 32 (0x20).

When blanking is enabled, only transparent (Phase 1) memory accesses are required, permitting full processor utilization of the system bus. However, MOB data will be accessed if the MOBS are not also disabled.

DISPLAY ROW/COLUMN SELECT

The normal display space consists of 25 cows of 40 character regions per row. For special display purposes, the display window may be reduced to 24 rows or 38 characters.

There is no change in the format of the displayed information, except that characters (bits) adjacent to the exterior border area are covered by the border.

The RSEL bit is in register 17 (0x11) and the CSEL bit is in register 22 (0x16). For standard display the larger display window is normally used, while the smaller display window is normally used in conjunction with scrolling.

SCROLLING

The display data may be scrolled up to one character region in both the horizontal and vertical direction.

When used in conjunction with the smaller display window (above), scrolling can be used to create a smooth panning motion of display data while updating the system memory only when a new character row (or column) is required.

Scrolling is also used for centering a display within the screen.

LIGHT PEN

The light pen input latches the current screen position into a pair of registers.(LPX,LPY) on a low-going edge. The X position register 19 (0x13) contains the 8 MSB of the X position at the time of transition. Since the X position is defined by a 9 bit coulter, resolution to 2 horizontal dots is provided. Similarly, the Y position is latched in its register 20 (0x14) with 8 bits provide unique raster resolution within the visible display. The light pen latch may be triggered only once per frame, and subsequent triggers within the same frame will have no effect.

RASTER REGISTER

The raster register is a dual function register. A read of the raster register 18 (0x12) returns the lower 3 bits of the current raster positon (the MSB-RC8 is located in register 17 (0x11)). A write to the raster bits (including RC8) is latched for use in an internal raster compare. When the current raster matches the written value, the raster interrupt latch is set. The raster register should be interrogated to prevent display flicker by delaying display changes to occur outside the visible area. The visible area of the display is from raster 51 to raster 251 (0x033-0x0FB).

INTERRUPT REGISTER

The interrupt register indicates the status of the four sources of interrupt. An interrupt latch in register 25 (0x19) is set to "I" when an interrupt source has generated an interrupt request.

To enable an interrupt request to set the IRQ/ output to •'0", the corresponding interrupt enable bit in register 26 (0x1A) must be set to "I”. Once an interrupt latch has been set, the latch may be cleared only by writing a "1" to the associated bit in the interrupt register. This feature allows selective handling of video interrupts without software storing of the active interrupts.

DYNAMIC RAM REFRESH

A dynamic ram refresh controller is built in to the 6567 device. Five 8-bit row addresses are refreshed every raster line.

This rate guarantees a maximum delay of 2.02 ms between the refresh of any single row address in a 128 refresh scheme. (The maximum delay is 3.66ms in a 256 address refresh scheme).

This refresh is totally transparent to the system, since the refresh occurs during Phase 1 of the system clock.

The 6567 generates both SAS and CAS which are normally connected directly to the dynamic rams. RAS and CAS are generated for every Phase 2 and every video data access (including refresh) so that external clock generation is not required.

COLOR CODE TABLE

SCREEN POSITION DECODES

HORIZONTAL DECODES

VERTICAL DECODES

Register Map

NOTE: All dashes read as "1" regardless of written value.

SYSTEM INTFERACE

The 6567vidso controller device interacts with the system data bus in a unique way. a 65XX system requires the system busses only during the Phase 2 (clock high) portion of the cycle. The 6567 device takes advantage of this characteristic by normally accessing system memory only during the Phase 1 (clock low) portion of the clock cycle. Therefore, operations such as character data fetches and memory refresh are totally transparent to the processor and do not reduce the processor through-put. The video chip provides the interface control signals required to maintain this bus sharing.

BUSS MUTLIPLEXING

The video circuit provides the AEC signal (address enable control) which is used to disable the processor address bus drivers, thereby allowing the video device to access the address bus. AEC is active low which permits direct connection to the AEC input of the 65XX family. The AEC signal is activated during every Phase 1 so that processor operation is not normally affected. Because of this bus "sharing", all memory accesses must be completed in 1/2 cycle. Since the video chip provides a IMhz clock (which should be used as system phase 2), a memory cycle is 500ns including address setup, data access and data setup to the reading device.

DMA OPERATION

Certain operations of the 6567require data at a faster rate than available by reading only during the Phase 1 time; specifically, the access of character pointers from the video matrix and the fetch of MIB data. Therefore, the processor must be disabled and the data accessed during the Phase 2 clock. This is accomplished via the BA (bus available) signal. The BA line is normally high but is brought low during Phase 1 to indicate that the video chip will require a Phase 2 data access. Three Phase 2 times are allowed after BA low for the processor to complete any current memory accesses. On the fourth Phase 2 after BA low, the AEC signal will remain low during Phase 2 as the video chip fetches data. The BA line is normally connected to the RDY input of a 65XX processor. The character pointer fetches occur every eighth raster line during the display window and require 40 consecutive Phase 2 accesses to fetch the video matrix pointers.

The MIB pointers are fetched every other Phase 1 at the end of each raster line. As needed, additional cycles are used for MIB data fetches, with all necessary bus control provided by the 8562 device.

INTERFACE SIGNAL DESCRIPTION

DATA BUS (D₇…D₀)

The eight data bus pins are the bi-directional data port, controlled by CS, R/W, and Phase₀.

The data bus can only be accessed while AEC and Phase₀ are high and CS is low.

CHIP SELECT (CS)

The chip select pin, CS, is brought low to enable access to the circuit registers in conjunction with the address and R/W pins.

CS low is recognized only while AEC and Phase₀ are high.

READ/WRITE (R/W)

The read/write input, R/W, is used to determine the direction of data transfer on the data bus, in conjunction with CS.

When R/W is high ("1") data is transferred from the selected register to the data bus output.

When R/W is low ("0") data presented on the data bus pins is loaded into the selected register.

ADDRESS BUS (A₁₀…A₀)

Address pins A₆-A₀ are multiplexed to allow direct connection to dynamic RAMs.

During the row address time, A₆-A₀ are driven on pins A₆-A₀, while A₁₃-A₈ are driven on pins A₅-A₀ and pin A₆ is "1" during the column time. A₁₀-A₇ is stable for the entire memory cycle. The lower six address pins, A₅-A₀, are also bi-directional. During a processor read or write of the video device, address pins A₅-A₀0 are inputs which latch on the low edge of RAS. The data on these address inputs selects the register for read or write as defined in the register map

CLOCK OUT

The clock output, Phase₀, is the 1Mhz clock used as the 65XX processor Phase₀ in. All system bus activity is referenced to this clock. The clock frequency is generated by dividing the 8Mhz video input clock by eight.

RAS / CAS

The RAS and CAS signals provide the timing signals necessary for dynamic RAMs. These signals are provided twice each clock out cycle to support a memory cycle during both phase 1 and phase 2.

INTERRUPTS (IRQ)

The interrupt output, IRQ, is brought low when an enabled source of interrupt occurs with in the device. The IRQ output is open drain, requiring an external pull-up resistor.

VIDEO INTERFACE

The video output from the 6567 consists of two signals which must be externally mixed together to create NTSC compatible composite video. After appropriate mixing, the resulting signal can directly drive a video monitor or RF modulator for use with a standard television.

VIDEO CLOCK IN

This clock input is the fundamental dot shift rate clock. In addition, all other video sync and system interface signals are derived by dividing this clock. Normally, the desired frequency is 9 Mhz. The primary constaints are the system timing and the requirement that one horizontal raster line is 520 video clock cycles

COLOR CLOCK IN

The color clock is used to derive the chrominance signal. NTSC video systems require this input to be 14.31818 Mhz. This base frequency is divided by 4 internally and then appropriately phase shifted to create the 3.5795 Mhz video color signal for NTSC applications.

SYNC/LUM OUTPUT

SYNC/LUM output from the 6567 contains all the video data, including horizontal and vertical syncs, as well as the luminance information of the video display. It is an open drain output requiring an external pull-up of 500 ohms.

COLOR OUTPUT

The COLOR output contains all the chrominance information, including the color reference burst and the color of all display data. The COLOR output is open source and should be terminated with 1,000 ohms to ground.

ELECTRICAL REQUIREMENTS

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed may cause permanent damage to the circuit. This is a stress rating only. Functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied.

OPERATING CONDITIONS

All electrical characteristics (A.C. and D.C.) are specified over the entire range of the operating conditions unless specifically noted.

A.C. CHARACTERISTICS

A.C. characteristic are specified with input waveforms between 0.4V input low level and 2.4V input high level and Dot Clock in of 8.182 Mhz. Outputs are loaded at the rated D.C. currents and voltage with 60fcF total capacitive load (including fixturing). All time measurements of active signals are referenced to 1.5V on inputs and outputs. Time measurements of high impedance signals are referenced to Vol and Voh levels.

D.C. CHARACTERISTICS

6567 TIMING DIAGRAM

The SID is a mixed-signal integrated circuit, featuring both digital and analog circuitry. All control ports are digital, while the output ports are analog. The SID features three-voice synthesis, where each voice may use one of at least five different waveforms: pulse wave (with variable duty cycle), triangle wave, sawtooth wave, pseudorandom noise (called white noise in documentation), and certain complex/combined waveforms when multiple waveforms are selected simultaneously.

Due to imperfect manufacturing technologies of the time and poor separation between the analog and digital parts of the chip, the 6581's output (before the amplifier stage) was always slightly biased from the zero level. Each time the volume register was altered, an audible click was produced. By quickly adjusting the amplifier's gain through the main 4-bit volume register, this bias could be modulated as PCM, resulting in a "virtual" fourth channel allowing 4-bit digital sample playback.

The better manufacturing technology in the 8580 used in the later revisions of Commodore 64C and the Commodore 128 DCR caused the bias to almost entirely disappear, causing the digitized sound samples to become very quiet. Fortunately, the volume level could be mostly restored with either a hardware modification (biasing the audio-in pin), or more commonly a software trick involving using the Pulse waveform to intentionally recreate the required bias.

The software trick generally renders one voice temporarily unusable, although clever musical compositions can make this problem less noticeable. An excellent example of this quality improvement noticeably reducing a sampled channel can be found in the introduction to Electronic Arts' game Skate or Die (1987). The guitar riff played is all but missing when played on the Commodore 64c or the Commodore 128.

The 6581 and 8580 differ from each other in several ways. The original 6581 was manufactured using the older NMOS process, which used 12V DC to operate.

The 8580 was made using the HMOS-II process, which requires less power (9V DC), and therefore makes the IC run cooler. The 8580 is thus far more durable than the 6581.

Also, due to more stable waveform generators, the bit-mixing effects are less noticeable and thus the combined waveforms come close to matching the original SID specification (which stated that they will be combined as a binary AND). The filter is also very different between the two models, with the 6581 cutoff range being a relatively straight line on a log scale, while the cutoff range on the 8580 is a straight line on a linear scale, and is close to the designers' actual specifications. Additionally, a better separation between the analog and the digital circuits made the 8580's output less noisy and distorted. The noise in 6xxx-series systems can be reduced by disconnecting the audio-in pin.

The consumer version of the 8580 was rebadged the 6582, even though the die on the chip is identical to a stock 8580 chip, including the '8580R5' mark. Dr. Evil Laboratories used it in their SID Symphony expansion cartridge (sold to Creative Micro Designs in 1991), and it was used in a few other places as well, including one PC sound-card.

Despite its documented shortcomings, many SID musicians prefer the flawed 6581 chip over the corrected 8580 chip. The main reason for this is that the filter produces strong distortion that is sometimes used to produce simulation of instruments such as a distorted electric guitar. Also, the highpass component of the filter was mixed in 3 dB attenuated compared to the other outputs, making the sound more bassy. In addition to nonlinearities in filter, the D/A circuitry used in the waveform generators produces yet more additional distortion that made its sound richer in character.

Source: Wikipedia: MOS Technology 6581

The μPD7002 is a high performance, low power monolithic CMOS A/D converter designed for microprocessor applications. The Analogue input voltage is applied to one of the 4 analog inputs.

By loading the input register with the multiplexer channel & the desired resolution of 8 or 12 bits, the integrating A/D conversion sequence is started.

At the end of the conversion the EOC signal goes low and if connected to the interrupt line of a microprocessor will cause an interrupt. At this point the digital data can be read in two bytes from the output registers.

The μPD7002 also features a status register that can be read at any time.

The μPD7002 is the A/D converter used by the BBC Microcomputer.

These devices contain 4 independent 2-input NAND gates. The open-collector outputs require pull-up resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher V_OH levels.

The TI SN5401 & SN54LS01 operate over the full military temperature range of -55°C to 125°C. The SN7401 & SN74LS01 operate over 0°C to 70°C.

These devices contain 6 hex inverters.

The TI SN5404 & SN54LS04 operate over the full military temperature range of -55°C to 125°C. The SN7404 & SN74LS04 operate over 0°C to 70°C.

These devices contain 6 hex inverters.

The TI SN5405 & SN54LS05 operate over the full military temperature range of -55°C to 125°C. The SN7405 & SN74LS05 operate over 0°C to 70°C.

These devices contain 6 hex inverters with High-Voltage Open Collectors. The outputs are rated at 30V.

The TI SN5405 & SN54LS05 operate over the full military temperature range of -55°C to 125°C. The SN7405 & SN74LS05 operate over 0°C to 70°C.

The 74240 provides Octal Buffers and Line Drivers With 3-State Outputs.

They are organized as two 4-bit buffers and drivers with separate output-enable (G) inputs. When G is low, the device passes data from the A inputs to the Y outputs. When G is high, the outputs are in the high impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment. To ensure the high-impedance state during power up or power down, G must be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 74241 provides Octal Buffers and Line Drivers With 3-State Outputs.

They are organized as two 4-bit buffers and drivers with separate output-enable (G) inputs. When G is low, the device passes data from the A inputs to the Y outputs. When G is high, the outputs are in the high impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment. To ensure the high-impedance state during power up or power down, G must be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 74244 provide Octal Buffers and Line Drivers With 3-State Outputs.

They are organized as two 4-bit buffers and drivers with separate output-enable (G) inputs. When G is low, the device passes data from the A inputs to the Y outputs. When G is high, the outputs are in the high impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment. To ensure the high-impedance state during power up or power down, G must be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 88LS120 is a dual differential, TTL compatible, line receiver for both balanced and unbalanced data transmission. The device features hysteresis and a response control for applications where controlled rise and falltimes and/or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe protection, should the input be open or short circuited. Each receiver includes an optional 180Ω terminating resistor and the output gate contains a logic strobe for time discrimination.