The memory of the 128K and +2 is organised like below. Note the +2A and +3 are different.
0000 3FFF |
ROM 0 128k Editor |
ROM 1 48K Basic |
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40007FFF | Bank 5 Screen #1 |
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8000 BFFF |
Bank 2 |
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C000 FFFF |
Bank 0 |
Bank 1 |
Bank 2 |
Bank 3 |
Bank 4 |
Bank 5 Screen #1 |
Bank 6 |
Bank 7 Screen #2 |
RAM Banks 1, 3, 4 and 6 and most of 7 are used for the ram disk. The rest of bank 7 contains editor scratch pads.
The memory is paged by writing to port 0x7FFD.
This port is write only, so a copy is stored in ram at address 0x5B5C.
Port | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Ram Copy |
---|---|---|---|---|---|---|---|---|---|
7FFD | DIS | ROM | SCR | RAM | 5B5C |
- RAM - The ram bank to page into 0xC000…0x7FFFF
- SCR set to 0 to display screen #1 in bank 5.[3] Set to 1 to display screen #2 in bank 7.[4]
- ROM set selects the 48K Basic rom, clear the 128K editor.
- DIS if set disables ram paging so that extra memory cannot be used in 48K mode. Once set it cannot be disabled until the machine is reset.
Typical bank switch on a 128:
LDA,(0x5B5C)Get previous port value
AND0xF8
OR4Select bank 4
LDBC,0x7FFDPort address
DIDisable interrupts
LD(0x5B5C),AUpdate memory copy of port
OUT(C),A
EIEnable interrupts
Notes:
- Odd ram banks are contended with the ULA (even though it can only use banks 5 and 7).
- Even banks are not contended so time critical code should run within those banks.
- Bank 5 is always mapped at 4000 and Bank 2 at 8000 regardless of what bank is mapped at C000
- Selecting the alternate screen in Bank 7 only tells the ULA to use it. It will not be placed at 4000