ADD

Tags:

Adds the source operand to the destination operand using binary addition and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The mode of the instruction indicates which operand is the source and which is the destination, as well as the operand size.

Operation:ADD
Syntax:
ADD ea, Dn
ADD Dn, ea
Data Size:
Byte
Word
Long
Flags:
XNZVC
*****
X Set the same as the carry bit
N Set if the result is negative; cleared otherwise
Z Cleared if the result is nonzero; set if zero
V Set if an overflow occurs; cleared otherwise
C Set if a carry is generated; cleared otherwise
Format:
15141312111098 76543210
1101RegisterOp ModeEffective Address
Dir SizeMode Register

Op Mode:

DirOperation
0\( ea + D_n \longrightarrow D_n \)
1\( D_n + ea \longrightarrow ea \)
SizeOperation
00Byte
01Word
10Long

Op Mode
Dir Operation Size
0 \( ea + D_n \longrightarrow D_n \) 00 Byte
1 \( D_n + ea \longrightarrow ea \) 01 Word
10 Long
Effective Address— Determines the addressing mode
  1. If the location specified is a source operand, all addressing modes can be used as listed in the following table:
    Addressing Mode Mode Register Addressing Mode Mode Register
    Dn000Dn(xxx).W111000
    An [1]001An(xxx).L111001
    (An)010An#<data>111100
    (An)+011An
    -(An)100An
    (D16,An)101An(D16,PC)111010
    (D8,An,Xn)110An(D8,PC,Xn)111011
    1. Word and long only
  2. If the location specified is a destination operand, only memory alterable addressing modes can be used as listed in the following table:
    Addressing Mode Mode Register Addressing Mode Mode Register
    Dn‐‐(xxx).W111000
    An‐‐(xxx).L111001
    (An)010An#<data>‐‐
    (An)+011An
    -(An)100An
    (D16,An)101An(D16,PC)‐‐
    (D8,An,Xn)110An(D8,PC,Xn)‐‐
Note
  1. The Dn mode is used when the destination is a data register.
  2. The destination ea is invalid for a data register.
  3. ADDA is used when the destination is an address register.
  4. ADDI and ADDQ are used when the source is immediate data.
  5. Most assemblers handle the distinction between ADD, ADDI and ADDQ
Last modified June 10, 2022: instruction fields (f3b3701)