RES
Reset a specific bit
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| \(r_b \longleftarrow 0\) | ||||||||
| RES b, r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 1 | 0 | b | r | |||||
| \((HL)_b \longleftarrow 0\) | ||||||||
| RES b, (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 1 | 0 | b | 1 | 1 | 0 | |||
| \((IX+d)_b \longleftarrow 0\) | ||||||||
| RES b, (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 1 | 0 | b | 1 | 1 | 0 | |||
| \((IY+d)_b \longleftarrow 0\) | ||||||||
| RES b, (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 1 | 0 | b | 1 | 1 | 0 | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
| Value | b | |
|---|---|---|
| 0 | 000 | |
| 1 | 001 | |
| 2 | 010 | |
| 3 | 011 | |
| 4 | 100 | |
| 5 | 101 | |
| 6 | 110 | |
| 7 | 111 | |
Z is set if the specified bit in the source is 0, otherwise it is cleared.
Flags Affected
| None. |
Opcode Matrix
| Source | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
| RES 0 |
RES 0,A
CB8728 |
RES 0,B
CB8028 |
RES 0,C
CB8128 |
RES 0,D
CB8228 |
RES 0,E
CB8328 |
RES 0,H
CB8428 |
RES 0,L
CB8528 |
RES 0,(HL)
CB86215 |
RES 0,(IX+d)
DDCBnn86423 |
RES 0,(IY+d)
FDCBnn86423 |
| RES 1 |
RES 1,A
CB8F28 |
RES 1,B
CB8828 |
RES 1,C
CB8928 |
RES 1,D
CB8A28 |
RES 1,E
CB8B28 |
RES 1,H
CB8C28 |
RES 1,L
CB8D28 |
RES 1,(HL)
CB8E215 |
RES 1,(IX+d)
DDCBnn8E423 |
RES 1,(IY+d)
FDCBnn8E423 |
| RES 2 |
RES 2,A
CB9728 |
RES 2,B
CB9028 |
RES 2,C
CB9128 |
RES 2,D
CB9228 |
RES 2,E
CB9328 |
RES 2,H
CB9428 |
RES 2,L
CB9528 |
RES 2,(HL)
CB96215 |
RES 2,(IX+d)
DDCBnn96423 |
RES 2,(IY+d)
FDCBnn96423 |
| RES 3 |
RES 3,A
CB9F28 |
RES 3,B
CB9828 |
RES 3,C
CB9928 |
RES 3,D
CB9A28 |
RES 3,E
CB9B28 |
RES 3,H
CB9C28 |
RES 3,L
CB9D28 |
RES 3,(HL)
CB9E215 |
RES 3,(IX+d)
DDCBnn9E423 |
RES 3,(IY+d)
FDCBnn9E423 |
| RES 4 |
RES 4,A
CBA728 |
RES 4,B
CBA028 |
RES 4,C
CBA128 |
RES 4,D
CBA228 |
RES 4,E
CBA328 |
RES 4,H
CBA428 |
RES 4,L
CBA528 |
RES 4,(HL)
CBA6215 |
RES 4,(IX+d)
DDCBnnA6423 |
RES 4,(IY+d)
FDCBnnA6423 |
| RES 5 |
RES 5,A
CBAF28 |
RES 5,B
CBA828 |
RES 5,C
CBA928 |
RES 5,D
CBAA28 |
RES 5,E
CBAB28 |
RES 5,H
CBAC28 |
RES 5,L
CBAD28 |
RES 5,(HL)
CBAE215 |
RES 5,(IX+d)
DDCBnnAE423 |
RES 5,(IY+d)
FDCBnnAE423 |
| RES 6 |
RES 6,A
CBB728 |
RES 6,B
CBB028 |
RES 6,C
CBB128 |
RES 6,D
CBB228 |
RES 6,E
CBB328 |
RES 6,H
CBB428 |
RES 6,L
CBB528 |
RES 6,(HL)
CBB6215 |
RES 6,(IX+d)
DDCBnnB6423 |
RES 6,(IY+d)
FDCBnnB6423 |
| RES 7 |
RES 7,A
CBBF28 |
RES 7,B
CBB828 |
RES 7,C
CBB928 |
RES 7,D
CBBA28 |
RES 7,E
CBBB28 |
RES 7,H
CBBC28 |
RES 7,L
CBBD28 |
RES 7,(HL)
CBBE215 |
RES 7,(IX+d)
DDCBnnBE423 |
RES 7,(IY+d)
FDCBnnBE423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
Last modified November 16, 2021: Add flags to bit operations (f00f81d)