SET
Set a specific bit
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| \(r_b \longleftarrow 1\) | ||||||||
| SET b, r | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 1 | 1 | b | r | |||||
| \((HL)_b \longleftarrow 1\) | ||||||||
| SET b, (HL) | ||||||||
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| 1 | 1 | b | 1 | 1 | 0 | |||
| \((IX+d)_b \longleftarrow 1\) | ||||||||
| SET b, (IX+d) | ||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 1 | 1 | b | 1 | 1 | 0 | |||
| \((IY+d)_b \longleftarrow 1\) | ||||||||
| SET b, (IY+d) | ||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB |
| d | ||||||||
| 1 | 1 | b | 1 | 1 | 0 | |||
| Register | r |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E | 011 |
| H | 100 |
| L | 101 |
| A | 111 |
| Value | b | |
|---|---|---|
| 0 | 000 | |
| 1 | 001 | |
| 2 | 010 | |
| 3 | 011 | |
| 4 | 100 | |
| 5 | 101 | |
| 6 | 110 | |
| 7 | 111 | |
Z is set if the specified bit in the source is 0, otherwise it is cleared.
Flags Affected
| None. |
Opcode Matrix
| Source | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| A | B | C | D | E | H | L | (HL) | (IX+d) | (IY+d) | |
| SET 0 |
SET 0,A
CBC728 |
SET 0,B
CBC028 |
SET 0,C
CBC128 |
SET 0,D
CBC228 |
SET 0,E
CBC328 |
SET 0,H
CBC428 |
SET 0,L
CBC528 |
SET 0,(HL)
CBC6215 |
SET 0,(IX+d)
DDCBnnC6423 |
SET 0,(IY+d)
FDCBnnC6423 |
| SET 1 |
SET 1,A
CBCF28 |
SET 1,B
CBC828 |
SET 1,C
CBC928 |
SET 1,D
CBCA28 |
SET 1,E
CBCB28 |
SET 1,H
CBCC28 |
SET 1,L
CBCD28 |
SET 1,(HL)
CBCE215 |
SET 1,(IX+d)
DDCBnnCE423 |
SET 1,(IY+d)
FDCBnnCE423 |
| SET 2 |
SET 2,A
CBD728 |
SET 2,B
CBD028 |
SET 2,C
CBD128 |
SET 2,D
CBD228 |
SET 2,E
CBD328 |
SET 2,H
CBD428 |
SET 2,L
CBD528 |
SET 2,(HL)
CBD6215 |
SET 2,(IX+d)
DDCBnnD6423 |
SET 2,(IY+d)
FDCBnnD6423 |
| SET 3 |
SET 3,A
CBDF28 |
SET 3,B
CBD828 |
SET 3,C
CBD928 |
SET 3,D
CBDA28 |
SET 3,E
CBDB28 |
SET 3,H
CBDC28 |
SET 3,L
CBDD28 |
SET 3,(HL)
CBDE215 |
SET 3,(IX+d)
DDCBnnDE423 |
SET 3,(IY+d)
FDCBnnDE423 |
| SET 4 |
SET 4,A
CBE728 |
SET 4,B
CBE028 |
SET 4,C
CBE128 |
SET 4,D
CBE228 |
SET 4,E
CBE328 |
SET 4,H
CBE428 |
SET 4,L
CBE528 |
SET 4,(HL)
CBE6215 |
SET 4,(IX+d)
DDCBnnE6423 |
SET 4,(IY+d)
FDCBnnE6423 |
| SET 5 |
SET 5,A
CBEF28 |
SET 5,B
CBE828 |
SET 5,C
CBE928 |
SET 5,D
CBEA28 |
SET 5,E
CBEB28 |
SET 5,H
CBEC28 |
SET 5,L
CBED28 |
SET 5,(HL)
CBEE215 |
SET 5,(IX+d)
DDCBnnEE423 |
SET 5,(IY+d)
FDCBnnEE423 |
| SET 6 |
SET 6,A
CBF728 |
SET 6,B
CBF028 |
SET 6,C
CBF128 |
SET 6,D
CBF228 |
SET 6,E
CBF328 |
SET 6,H
CBF428 |
SET 6,L
CBF528 |
SET 6,(HL)
CBF6215 |
SET 6,(IX+d)
DDCBnnF6423 |
SET 6,(IY+d)
FDCBnnF6423 |
| SET 7 |
SET 7,A
CBFF28 |
SET 7,B
CBF828 |
SET 7,C
CBF928 |
SET 7,D
CBFA28 |
SET 7,E
CBFB28 |
SET 7,H
CBFC28 |
SET 7,L
CBFD28 |
SET 7,(HL)
CBFE215 |
SET 7,(IX+d)
DDCBnnFE423 |
SET 7,(IY+d)
FDCBnnFE423 |
|
Instruction
Opcode hexSize bytesCycle count
| Register | Memory |
Last modified November 16, 2021: Add flags to bit operations (f00f81d)