LD (nn), s
Store register into memory via address
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
---|---|---|---|---|---|---|---|---|
\((nn) \longleftarrow A\) | ||||||||
LD (nn), A | ||||||||
0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 32 |
7 | nn | 0 | ||||||
15 | 8 | |||||||
\((nn+1) \longleftarrow dd_h, (nn) \longleftarrow dd_l\) | ||||||||
LD (nn), dd | ||||||||
1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
0 | 1 | dd | 0 | 0 | 1 | 1 | ||
7 | nn | 0 | ||||||
15 | 8 | |||||||
\((nn+1) \longleftarrow H, (nn) \longleftarrow L\) | ||||||||
LD (nn), HL | ||||||||
0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 22 |
7 | nn | 0 | ||||||
15 | 8 | |||||||
\((nn+1) \longleftarrow IX_h, (nn) \longleftarrow IX_l\) | ||||||||
LD (nn), IX | ||||||||
1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 22 |
7 | nn | 0 | ||||||
15 | 8 | |||||||
\((nn+1) \longleftarrow IY_h, (nn) \longleftarrow IY_l\) | ||||||||
LD (nn), IY | ||||||||
1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 22 |
7 | nn | 0 | ||||||
15 | 8 |
Value | dd |
---|---|
00 | BC |
01 | DE |
10 | HL |
11 | SP |
Flags Affected
None. |
Opcode Matrix
A | BC | DE | HL | IX | IY | SP | |
---|---|---|---|---|---|---|---|
(nn) |
LD (nn), A
32nnnn313 |
|
|
LD (nn), HL
22nnnn316 |
|
|
|
(nn) |
|
LD (nn), BC
ED43nnnn420 |
LD (nn), DE
ED53nnnn420 |
LD (nn), HL
ED63nnnn420 |
LD (nn), IX
DD22nnnn420 |
LD (nn), IY
FD22nnnn420 |
LD (nn), SP
ED73nnnn420 |
Instruction
Opcode hexSize bytesCycle count
| Memory |
Last modified November 16, 2021: Update flag rendering so it can be reused for the Z80 (06001ea)