Timing

How the system clock relates to processor speed

The Z80 processor executes instructions as a series of basic operations:

  • Memory access
  • I/O device access
  • Interrupt acknowledge

Each of these operations is known as a Machine cycle (M-cycle), which can take between 3 and 6 T-Cycles to execute, although this can be extended by the WAIT signal. A T-cycle (Time Cycle) is one cycle of the system clock.

The following diagram shows an example of a single instruction that reads from memory and writes back.

Visualisation of the timing of a single CPU instruction

Opcode fetch

The Opcode fetch takes 4 T-cycles:

Visualisation of the timing of fetching an opcode

T1 Sets the Address bus A0…15 to the current value of the program counter.
T2 Reads the opcode during the second half of the cycle.
T3 and T4 has the refresh address set on the Address Bus. This is to allow dynamic ram to be refreshed.

Memory Access

Memory access cycles are generally three T-cycles long unless wait states are requested by memory via the WAIT signal.

Memory Read Cycle

For a memory read the MREQ and RD signals are pulled low once the address bus is stable.

Visualisation of the timing of reading from memory

Memory Write Cycle

For a memory write the MREQ and WR signals are pulled low once the address bus is stable.

Visualisation of the timing of writing to memory

WR goes inactive half a T-State before the address and data bus contents are changed to support different types of memory.

I/O Cycles

I/O operations are similar to memory, except the IORQ signal is used instead of MREQ to indicate that devices not memory should respond.

Also an additional wait state is inserted after T-State 2. The reason for this single wait state insertion is that during I/O operations, the period from when the IORQ signal goes active until the CPU must sample the WAIT line is short. Without this extra state, sufficient time does not exist for an I/O port to decode its address and activate the WAIT line if a wait is required. Additionally, without this wait state, it is difficult to design MOS I/O devices that can operate at full CPU speed. During this wait state period, the WAIT request signal is sampled.

I/O Read Cycle

During a read I/O operation, the RD line is used to enable the addressed port onto the data bus, just as in the case of a memory read.

Visualisation of the timing of reading from a device

I/O Write Cycle

During a write I/O operation, the WR line is used to enable the addressed port onto the data bus, just as in the case of a memory write.

Visualisation of the timing of writing to a device
Last modified November 15, 2021: Add resources, fix title of iowrite.svg (4b1f2ec)