Pin Layout
General pins
A0…A15 Address Bus
Address Bus (output, active High, tristate). A0…A15 form a 16-bit Address Bus, which provides the addresses for memory data bus exchanges (up to 64 KB) and for I/O device exchanges.
D0…D7 Data Bus
D0…D7 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.
CLK Clock (input)
Single-phase MOS-level clock.
System Control
M1 Machine Cycle One (output, active Low)
M1, together with MREQ, indicates that the current machine cycle is the op code fetch cycle of an instruction execution. M1, when operating together with IORQ, indicates an interrupt acknowledge cycle.
MREQ Memory Request (output, active Low, tristate)
MREQ indicates that the address bus holds a valid address for a memory read or a memory write operation.
IORQ Input/Output Request (output, active Low, tristate)
IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.
RD Read (output, active Low, tristate)
RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.
WR Write (output, active Low, tristate)
WR indicates that the CPU data bus contains valid data to be stored at the addressed memory or I/O location.
RFSH Refresh (output, active Low)
RFSH, together with MREQ, indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.
Bus Control
BUSACK Bus Acknowledge
The BUSACK pin indicates to the requesting device that the CPU address bus, data bus and control signals MREQ, IORQ, RD and WR have entered their high-impedance states and other devices on the bus can control those lines.
BUSREQ Bus Request
BUSREQ contains a higher priority than NMI and is always recognized at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD and WR to enter a high-impedance state so that other devices can control these lines. BUSREQ is normally wired OR and requires an external pull-up for these applications.
Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAM.
CPU Control
HALT HALT State (output, active Low)
HALT indicates that the CPU has executed a HALT instruction and is waiting
for
either a nonmaskable or a maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refreshes.
WAIT WAIT (input, active Low)
WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.
INT Interrupt Request (input, active Low)
An Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and requires an external pull-up for these applications.
NMI Nonmaskable Interrupt (input, negative edge-triggered)
NMI contains a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066h.
RESET Reset (input, active Low)
RESET initializes the CPU as follows:
- it resets the interrupt enable flip-flop,
- clears the Program Counter and registers I and R,
- sets the interrupt status to Mode 0.
During reset time, the address and data bus enter a high-impedance state, and all control output signals enter an inactive state. RESET must be active for a minimum of three full clock cycles before a reset operation is complete.